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The increasing demand on wireless networks to provide faster data links to customers has driven transceiver hardware to increasingly demanding performance with enough bandwidth to support the largest standardized multi-carrier frequency bands (with band aggregation in some cases) and enough receiver sensitivity and dynamic range to function in the presence of the strong blocking signals common in busy environments. This TI Design describes a RF receiver subsystem reference design with 16-bit sampler that achieves more than 100MHz of bandwidth including a down-converting mixer, digital variable gain amplifier (DVGA), high speed pipelined analog-to-digital converter (ADC), local oscillator (LO) RF synthesizer, and jitter-cleaning clock generator.
- Implements a RF Super-Heterodyne Receiver Subsystem with 700–2700-MHz Input Range, Wide 100-MHz IF Bandwidth and 16-Bit ADC
- Accelerate the Design Time of a Wireless Communications, Software Defined Radio, Military, or Test and Measurement Application With a Proven IF Signal Chain
- Evaluate this Reference Design Effortlessly With Supported Data Capture and Analysis Tools
- This Reference Design is Tested and Includes an Evaluation Module (EVM), Configuration Software, and User’s Guide