TIDA-01028

12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer

TIDA-01028

Design files

Overview

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves using the Noiseless Aperture Delay Adjustment (tAD Adjust) feature of the ADC12DJ3200. This feature is also used to minimize mismatches typical of interleaved ADCs: maximizing SNR, ENOB and SFDR performance. A low-phase noise clocking tree with JESD204B support is also featured on this reference design. It is implemented using the LMX2594 wideband PLL and the LMK04828 synthesizer and jitter cleaner.

Features
  • Sampling rate up to 12.8 GSPS, using time interleaved 12-bit RF-sampling ADCs
  • Analog front end support up to 6-GHz bandwidth
  • Fine sample clock phase adjustment (19-fs resolution)
  • Phase synchronization of multiple ADCs
  • Companion power reference design with a >85% efficiency at 12-V input
  • JESD204B supporting 8-, 16-, or 32-JESD lanes and data rates up to 12.8 Gbps per lane
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDUEI2.PDF (6295 K)

Reference design overview and verified performance test data

TIDRZ70.PDF (4789 K)

Detailed schematic diagram for design layout and components

TIDRZ71A.PDF (240 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRZ72.PDF (2940 K)

Detailed overview of design layout for component placement

TIDRZ74.ZIP (41928 K)

Files used for 3D models or 2D drawings of IC components

TIDCFC2.ZIP (13521 K)

Design file that contains information on physical board layer of design PCB

TIDRZ73.PDF (28699 K)

PCB layer plot file used for generating PCB design layout

Products

Includes TI products in the design and potential alternatives.

AND gates

SN74LVC1G081-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate

Data sheet: PDF
Analog switches & muxes

SN74LVC2G535-V, 2:1 (SPDT), 1-channel general-purpose analog switch (available in the NanoFree™ package)

Data sheet: PDF | HTML
Buck modules (integrated inductor)

TPS8213017-V input 3-A step-down converter module with integrated inductor

Data sheet: PDF | HTML
Clock buffers

LMK003043.1-GHz differential clock buffer/level translator with 4 configurable outputs

Data sheet: PDF | HTML
Clock jitter cleaners & synchronizers

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
Comparators

LMC6762Dual Micro-Power Rail-to-Rail Input CMOS Comparator with Push-Pull Output

Data sheet: PDF
Digital temperature sensors

LM95233±2°C Dual Remote and Local Temperature Sensor with TruTherm Technology and SMBus Interface

Data sheet: PDF
Direction-controlled voltage translators

SN74AVC4T774Four-bit dual-supply bus transceiver with configurable voltage-level shifting and tri-state outputs

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADC12DJ320012-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADC12DJ5200RFRF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

Data sheet: PDF | HTML
I2C general-purpose I/Os (GPIOs)

TCA9534A8-bit 1.65- to 5.5-V I2C/SMBus I/O expander with interrupt, & config registers

Data sheet: PDF | HTML
LVDS, M-LVDS & PECL ICs

DS90LT012AQ-Q1Automotive LVDS differential line receiver

Data sheet: PDF
LVDS, M-LVDS & PECL ICs

DS90LV028AQ-Q1Automotive LVDS dual differential line receiver

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TLV702300-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A331-A, high-PSRR, negative, adjustable low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A83002-A, low-VIN, low-2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good wi

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A843-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good with high-accuracy

Data sheet: PDF | HTML
N-channel MOSFETs

CSD15571Q220-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 19.2 mOhm

Data sheet: PDF
Noninverting buffers & drivers

SN74LVC1G125Single 1.65-V to 5.5-V buffer with 3-state outputs

Data sheet: PDF | HTML
Oscillators

LMK61E2156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

Data sheet: PDF | HTML
RF FDAs

LMH54018-GHz Ultra wideband fully differential amplifier

Data sheet: PDF | HTML
RF PLLs & synthesizers

LMX259415-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support

Data sheet: PDF | HTML
RF VGAs

LMH64014.5 GHz ultra wideband digital variable gain amplifier

Data sheet: PDF | HTML
eFuses & hot swap controllers

TPS259264.5-V to 13.8-V, 30mΩ, 2-5A eFuse

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide Mar. 05, 2019
Technical article Step-by-step considerations for designing wide-bandwidth multichannel systems PDF | HTML Jun. 04, 2019
White paper Interleaving ADCs for Higher Sample Rates Feb. 01, 2005
Application note Defining Skew, Propagation-Delay, Phase Offset (Phase Error) Nov. 28, 2001

Related design resources

Hardware development

EVALUATION BOARD
ADC12DJ3200EVM ADC12DJ3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module TSW14J57EVM Data capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps

Reference designs

REFERENCE DESIGN
TIDA-01027 Low-noise power supply reference design maximizing performance in 12.8-GSPS data acquisition systems

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