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- Ref Design Optimizing FPGA and Data Throughput for High Channel Auto Testers
(PDF 6791 KB)
10 Apr 2017
- TIDA-01051 Schematic and Block Diagram
(PDF 2807 KB)
30 Mar 2017
The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such as TI’s DS90C383B, to combine many simultaneously sampling ADC outputs into several LVDS lines dramatically reduces the number of pins the host FPGA must process. As a result, a single FPGA can process a significantly increased number of DAQ channels and board routing complexity is greatly reduced.
- Two 20 bit SAR ADC channels (expendable up to 28)
- Three level MUX tree (up to 64 channels per ADC)
- Highlights throughput improvements using serialized ADC output data
- Modular front-end reference design for high channel count systems that can be repeated
- Up to +/-12V input signal (+/-24Vpp differential)