Data Capture / Pattern Generator: Data Converter EVMs With 8 JESD204B Lanes From 0.6-12.5Gbps
- TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C)
(PDF 6664 KB)
11 Jan 2016 1,024 views
The Texas Instruments TSW14J56 Evaluation Module (EVM) is a next generation of pattern generator and data capture card used to evaluate performances of the new Texas Instruments (TI) JESD204B family of high-speed analog-to-digital converters (ADC) and digital-to-analog converters (DAC).
Populated with an Arria V GZ device and using Altera’s JESD204B IP solution, the TSW14J56 can be dynamically configurable to support all lanes speeds from 600Mbps to 12.5Gbps, from 1 to 8 lanes, 1 to 16 converters, and 1 to 4 octets per frame.
Together with the accompanying High Speed Data Converter Pro Graphic User Interface (GUI), it is a complete system that captures and evaluates data samples from ADC EVM’s and generates and sends desired test patterns to DAC EVM’s.
- Quickly evaluate JESD204B DAC and ADC performance using TI High Speed Data Converter Pro software
- Direct connection to all TI JESD204B High Speed Data Converter EVM’s using an FMC standard connector
- Quarter rate DDR3 controllers supporting up to 800MHz DDR3 operation
- JESD RX and TX IP cores with 10 routed transceiver channels
- Many available general purpose IO’s (status signals, SPI interface, etc.) between the FPGA and the FMC connector
- SPI/JTAG reconfigurable JESD core parameters: L,M,K,F,HD,S etc.
- Support for SUBCLASS 0 and 1 operation
- Dynamically reconfigurable transceiver data rate using HSDC Pro software.
- Operating range from 0.611Gbps to 12.5Gbps
- An onboard high-speed USB 3.0 to parallel converter bridges the FPGA interface to the host PC and GUI
- 32 Gb DDR3 SDRAM (total of 2G 16-bit samples).