Serializer/Deserializer (SerDes)
Texas Instruments offers a complete portfolio of gigabit serial transceivers using serializers and deserialzers with speeds ranging from 0.1 Gbps to 10+ Gbps.
The family of SerDes devices from TI provides low power dissipation while enabling multi-gigabit transmission over copper backplanes, cable and optical links. The transceivers can be used in a variety of communications applications, including Gigabit Ethernet, 10 Gigabit Ethernet modules, Ethernet PON (Passive Optical Networking), synchronous optical network OC-48 and OC-192 based equipment, CPRI and OBSAI wireless infrastructure backplanes, display and imaging interfaces, and many other applications.
NEW! TLK10034 – Industry's first all-in-one transceiver for 10 Gbps Ethernet standards
- Multiple protocol flexibility: Each of the four bi-directional channels support 10GBASE-KR, XAUI, 1GBASE-KX, CPRI, and OBSAI standard protocols
- Optimized link performance: Link training seamlessly brings up the link and optimizes the transmitter pre-emphasis levels minimizing system BER
- Reduced power consumption: Consumes 825 mW/channel (typ), compared to competitive SerDes that consume more than 1 W
- Higher signal integrity: FEC manages the signal integrity performance by compensating up to 29 dB insertion loss at 6 GHz to improve BER and system margin
| Parameter | LVDS Ser/Des (<100MHz) | Channel Link (I) |
Channel Link II |
Channel Link III |
Gigabit Ethernet/ Fibre Channel |
FPGA-Link | General Purpose Gigabit | SONET/ Optical |
10G | |
| Serial Interface | Max Speed/CH | 2.5 Gbps | 6.384 Gbps | 2.7 Gbps | 1 Gbps | 2.6 Gbps | 3.125 Gbps | 6.25 Gbps | OC-48 with FEC | 10 Gbps |
| I/O | LVDS/BLVDS | LVDS | LVDS/CML | LVDS/CML | LVPECL/VML | CML | CML/VML | PECL | CML/LVPECL | |
| Clock | Embedded Clock | Parallel Clock | Embedded Clock | Embedded Clock & Control | 8b/10b | |||||
| Cable Reach | Short (up to 10m) | Medium (up to 20m) | Short (up to 10m) | |||||||
| Parallel Interface | I/O | LVCMOS | LVCMOS | LVCMOS , LVDS | LVCMOS | LVCMOS | LVDS | LVCMOS, HSTL | LVDS/PECL | LVCMOS, HSTL, SSTL, CML |
| Bits | 10, 15, 16, 18, 21, 28 | 14, 21, 28, 48 | 24, 32 4+clk (LVDS) | 16, 21 | 10, 16, 20 | 5 | 8, 10, 16, 18, 20 | 4 | 4, 8, 10, 20, 32 | |
| Bus Speed | 10 – 135 MHz | 12 – 133 MHz | 5 – 85 MHz | 10 – 50 MHz | 100 – 130 MHz | 125 – 312.5 MHz | 30 – 307 MHz | 155/622 MHz | 30 – 425 MHz | |
| Typical Applications |
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| Links to Products | LVDS Ser/Des (<100MHz) | Channel Link (I) |
Channel Link II |
Channel Link III |
Gigabit Ethernet/ Fibre Channel |
FPGA-Link | General Purpose Gigabit | SONET/ Optical |
10G | |
SerDes Products
Data SerDes
- 10 Gigabit (XAUI) Ethernet Transceiver
- General Purpose Gigabit Transceiver
- Gigabit Ethernet/Fibre Channel Transceiver
- Sonet/Optical Transceiver
- Channel Link III (Embedded Clock & Control)
- Channel Link II (Embedded Clock)
- Channel Link (I) (Parallel Clock)
- FPGA-Link
- LVDS SerDes (<100 MHz)
- Industrial High Voltage Input SerDes
Display/Video SerDes
- FPD-Link III Ser/Des (Embedded Clock & Control)
- FPD-Link II Ser/Des (Embedded Clock)
- FlatLink & FPD-Link I (Parallel Clock)
- FlatLink3G (Parallel Clock)
- Portable Ser/Des (Mobile Pixel Link – MPL)
- PanelBus (DVI) (Parallel Clock)
- SDI SerDes (SMPTE)
Support Products
SerDes Design Resources
Featured SerDes App Notes
- Comparing Bus Solutions (Rev. B)
(slla067.pdf, 1795 Kbytes)
Oct 2009 Download
SerDes Design Guides
- LVDS Owner's Manual
- Low-Voltage Differential Signaling (LVDS) Design Notes
- LVDS Application and Data Handbook
Interface E2E Community

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