| Class |
Document |
Source |
Message |
Time |
Date |
No. |
| [Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Clearance Constraint: (Collision < 5mil) Between Pad FID1-1(2130mil,1160mil) on Top Layer And Arc (2130mil,1160mil) on Top Layer |
12:30:23 PM |
7/20/2018 |
1 |
| [Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Clearance Constraint: (Collision < 5mil) Between Pad FID2-1(680mil,1160mil) on Top Layer And Arc (680mil,1160mil) on Top Layer |
12:30:23 PM |
7/20/2018 |
2 |
| [Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Clearance Constraint: (Collision < 5mil) Between Pad FID3-1(2170mil,100mil) on Top Layer And Arc (2170mil,100mil) on Top Layer |
12:30:23 PM |
7/20/2018 |
3 |
| [Silk To Solder Mask Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Solder Mask Clearance Constraint: (2.049mil < 4mil) Between Track (1379.982mil,862.8mil)(1379.982mil,917.266mil) on Top Overlay And Via (1400mil,880mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [2.049mil] |
12:30:23 PM |
7/20/2018 |
4 |
| [Silk To Solder Mask Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Solder Mask Clearance Constraint: (2.049mil < 4mil) Between Track (1362.734mil,509.982mil)(1417.2mil,509.982mil) on Top Overlay And Via (1390mil,530mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [2.049mil] |
12:30:23 PM |
7/20/2018 |
5 |
| [Silk To Solder Mask Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Solder Mask Clearance Constraint: (3.031mil < 4mil) Between Text "C24" (850mil,100mil) on Top Overlay And Via (830mil,80mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.031mil] |
12:30:23 PM |
7/20/2018 |
6 |
| [Silk To Solder Mask Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Solder Mask Clearance Constraint: (3.327mil < 4mil) Between Track (987.266mil,114mil)(987.266mil,139.982mil) on Top Overlay And Via (980mil,160mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.327mil] |
12:30:23 PM |
7/20/2018 |
7 |
| [Silk To Solder Mask Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Solder Mask Clearance Constraint: (2.049mil < 4mil) Between Track (932.8mil,139.982mil)(987.266mil,139.982mil) on Top Overlay And Via (980mil,160mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [2.049mil] |
12:30:23 PM |
7/20/2018 |
8 |
| [Silk To Solder Mask Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Solder Mask Clearance Constraint: (3.031mil < 4mil) Between Text "C14" (1390mil,760mil) on Top Overlay And Via (1380mil,740mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.031mil] |
12:30:23 PM |
7/20/2018 |
9 |
| [Silk To Solder Mask Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Solder Mask Clearance Constraint: (2.832mil < 4mil) Between Track (1824.333mil,1059.2mil)(1850.315mil,1059.2mil) on Top Overlay And Via (1850mil,1080mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [2.832mil] |
12:30:23 PM |
7/20/2018 |
10 |
| [Silk To Solder Mask Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Solder Mask Clearance Constraint: (2.813mil < 5mil) Between Text "J2" (21mil,639mil) on Top Overlay And Pad J3-6(70mil,700mil) on Multi-Layer [Top Overlay] to [Top Solder] clearance [2.813mil] |
12:30:23 PM |
7/20/2018 |
11 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (2.479mil < 4mil) Between Text "C22" (990mil,530mil) on Top Overlay And Track (959.982mil,472.734mil)(959.982mil,527.2mil) on Top Overlay Silk Text to Silk Clearance [2.479mil] |
12:30:23 PM |
7/20/2018 |
12 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (2.479mil < 4mil) Between Text "C22" (990mil,530mil) on Top Overlay And Track (934mil,527.2mil)(959.982mil,527.2mil) on Top Overlay Silk Text to Silk Clearance [2.479mil] |
12:30:23 PM |
7/20/2018 |
13 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (3.742mil < 4mil) Between Text "C3" (1830mil,680mil) on Top Overlay And Track (1824.333mil,714.734mil)(1850.315mil,714.734mil) on Top Overlay Silk Text to Silk Clearance [3.742mil] |
12:30:23 PM |
7/20/2018 |
14 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (1.946mil < 4mil) Between Text "C27" (1590mil,290mil) on Top Overlay And Track (1534mil,362.8mil)(1559.982mil,362.8mil) on Top Overlay Silk Text to Silk Clearance [1.946mil] |
12:30:23 PM |
7/20/2018 |
15 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (1.946mil < 4mil) Between Text "C27" (1590mil,290mil) on Top Overlay And Track (1559.982mil,362.8mil)(1559.982mil,417.266mil) on Top Overlay Silk Text to Silk Clearance [1.946mil] |
12:30:23 PM |
7/20/2018 |
16 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (3.475mil < 4mil) Between Text "C26" (1870mil,350mil) on Top Overlay And Track (1845.569mil,384.099mil)(1871.551mil,384.099mil) on Top Overlay Silk Text to Silk Clearance [3.475mil] |
12:30:23 PM |
7/20/2018 |
17 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (3.56mil < 4mil) Between Text "C26" (1870mil,350mil) on Top Overlay And Track (1939.551mil,384.099mil)(1965.533mil,384.099mil) on Top Overlay Silk Text to Silk Clearance [3.56mil] |
12:30:23 PM |
7/20/2018 |
18 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (3.621mil < 4mil) Between Text "C16" (1288.504mil,378.504mil) on Top Overlay And Track (1264mil,412.734mil)(1289.982mil,412.734mil) on Top Overlay Silk Text to Silk Clearance [3.621mil] |
12:30:23 PM |
7/20/2018 |
19 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (3.621mil < 4mil) Between Text "C16" (1288.504mil,378.504mil) on Top Overlay And Track (1289.982mil,412.734mil)(1289.982mil,467.2mil) on Top Overlay Silk Text to Silk Clearance [3.621mil] |
12:30:23 PM |
7/20/2018 |
20 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (2.894mil < 4mil) Between Text "J2" (21mil,639mil) on Top Overlay And Track (20mil,659.842mil)(20mil,740.157mil) on Top Overlay Silk Text to Silk Clearance [2.894mil] |
12:30:23 PM |
7/20/2018 |
21 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (Collision < 4mil) Between Text "J2" (21mil,639mil) on Top Overlay And Track (39.685mil,650mil)(100.315mil,650mil) on Top Overlay Silk Text to Silk Clearance [0mil] |
12:30:23 PM |
7/20/2018 |
22 |
| [Silk To Silk Clearance Constraint Violation] |
PCB.PcbDoc |
Advanced PCB |
Silk To Silk Clearance Constraint: (Collision < 4mil) Between Text "J2" (21mil,639mil) on Top Overlay And Track (20mil,659.842mil)(39.685mil,650mil) on Top Overlay Silk Text to Silk Clearance [0mil] |
12:30:23 PM |
7/20/2018 |
23 |
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