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TDA2E

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SoC processors with graphics and video acceleration for ADAS applications (23mm package)

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Data sheet
Errata

TDA2E

ACTIVE
Data sheet Order now

Product details

Arm CPU 1 Arm Cortex-A15 Arm (max) (MHz) 500, 800 Coprocessors 4 Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 1 3D Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 2-Port 1Gb switch PCIe 2 PCIe Gen 3 Hardware accelerators 1 Image Video Accelerator Features Vision Analytics Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
Arm CPU 1 Arm Cortex-A15 Arm (max) (MHz) 500, 800 Coprocessors 4 Arm Cortex-M4 CPU 32-bit Graphics acceleration 1 2D, 1 3D Display type 1 HDMI, 3 LCD Protocols Ethernet Ethernet MAC 2-Port 1Gb switch PCIe 2 PCIe Gen 3 Hardware accelerators 1 Image Video Accelerator Features Vision Analytics Operating system Android, Linux, RTOS Security Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125
FCBGA (ABC) 760 529 mm² 23 x 23
  • Architecture designed for ADAS applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video inputs and video outputs
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP cores
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • DDR3/DDR3L External Memory Interface (EMIF) module
    • Supports up to DDR3-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Single-core PowerVR® SGX544 3D GPU
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-Port Gigabit Ethernet switch
    • Up to two external ports, one internal
  • Sixteen 32-bit general-purpose timers
  • 32-bit MPU watchdog timer
  • Six high speed Inter-Integrated Circuit (I2C™) ports
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad Serial Peripheral Interface (QSPI™)
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High Speed USB 2.0 dual-role device
  • High Speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital®/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® (PCIe®) revision 3.0 Port with integrated PHY
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • MIPI® Camera Serial Interface 2 (CSI-2)
  • Up to 215 General-Purpose I/O (GPIO) pins
  • Real-Time Clock subsystem (RTCSS)
  • Device Security Features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys (Silicon Revision 2.1)
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)
  • Architecture designed for ADAS applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video inputs and video outputs
  • Arm® Cortex®-A15 microprocessor subsystem
  • C66x floating-point VLIW DSP cores
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 × 16-bit fixed-point multiplies per cycle
  • Up to 512KB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • DDR3/DDR3L External Memory Interface (EMIF) module
    • Supports up to DDR3-1333 (667 MHz)
    • Up to 2GB across single chip select
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • IVA-HD subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Single-core PowerVR® SGX544 3D GPU
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Video Processing Engine (VPE)
  • One Video Input Port (VIP) module
    • Support for up to four multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-Port Gigabit Ethernet switch
    • Up to two external ports, one internal
  • Sixteen 32-bit general-purpose timers
  • 32-bit MPU watchdog timer
  • Six high speed Inter-Integrated Circuit (I2C™) ports
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad Serial Peripheral Interface (QSPI™)
  • SATA interface
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • High Speed USB 2.0 dual-role device
  • High Speed USB 2.0 on-the-go
  • Four MultiMedia Card/Secure Digital®/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® (PCIe®) revision 3.0 Port with integrated PHY
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • MIPI® Camera Serial Interface 2 (CSI-2)
  • Up to 215 General-Purpose I/O (GPIO) pins
  • Real-Time Clock subsystem (RTCSS)
  • Device Security Features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG lock
    • Secure keys
    • Secure ROM and boot
    • Customer programmable keys (Silicon Revision 2.1)
  • Power, reset, and clock management
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)

TI’s new TDA2Ex System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Ex family enables broad ADAS applications in today’s automobile by integrating an optimal mix of performance, low power, and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Ex SoC enables sophisticated embedded vision technology in today’s automobile by enabling a board range of ADAS applications including park assist, surround view and sensor fusion on a single architecture.

The TDA2Ex SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation core, Arm® Cortex®-A15 MPCore™ and dual-Arm® Cortex®-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerator for rendering virtual views, enable a 3D viewing experience. The TDA2Ex SoC also integrates a host of peripherals including multicamera interfaces (both parallel and serial, including CSI-2) to enable Ethernet or LVDS-based surround view systems, displays and GigB Ethernet AVB.

Additionally, TI provides a complete set of development tools for the Arm® and DSP, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment is available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Ex ADAS processor is qualified according to the AEC-Q100 standard.

TI’s new TDA2Ex System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Ex family enables broad ADAS applications in today’s automobile by integrating an optimal mix of performance, low power, and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Ex SoC enables sophisticated embedded vision technology in today’s automobile by enabling a board range of ADAS applications including park assist, surround view and sensor fusion on a single architecture.

The TDA2Ex SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation core, Arm® Cortex®-A15 MPCore™ and dual-Arm® Cortex®-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerator for rendering virtual views, enable a 3D viewing experience. The TDA2Ex SoC also integrates a host of peripherals including multicamera interfaces (both parallel and serial, including CSI-2) to enable Ethernet or LVDS-based surround view systems, displays and GigB Ethernet AVB.

Additionally, TI provides a complete set of development tools for the Arm® and DSP, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment is available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Ex ADAS processor is qualified according to the AEC-Q100 standard.
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More Information

This product family is available for high volume automotive manufacturers. Please contact your TI sales representative for more details.

Learn more about the TDA2E SoC for advanced driver assistance systems (ADAS).

Technical documentation

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Type Title Date
* Data sheet TDA2Ex SoC for Advanced Driver Assistance Systems (ADAS) 23mm Package (ABC Package) Silicon Revision 2.0 and 2.1 datasheet (Rev. H) PDF | HTML 24 Jul 2019
* Errata TDA2Ex SoC for Advanced Driver Assistance Systems (ADAS) Silicon Errata (Rev. D) 28 Feb 2017
White paper Paving the way to self-driving cars with ADAS (Rev. A) 24 Jul 2020
White paper Stereo vision- facing the challenges and seeing the opportunities for ADAS (Rev. A) 24 Jul 2020
Application note AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 06 Jan 2020
Application note TDA2x/TDA2E Performance (Rev. A) PDF | HTML 10 Jun 2019
User guide TDA2Ex SoC for Advanced Driver Assistance Systems (ADAS) TRM (Rev. D) 21 May 2019
EVM User's guide TDA2Ex-17 EVM CPU board user's guide (Rev. B) 11 Mar 2019
Application note The Implementation of YUV422 Output for SRV 02 Aug 2018
Application note MMC DLL Tuning (Rev. B) 31 Jul 2018
Application note Integrating AUTOSAR on TI SoC: Fundamentals 18 Jun 2018
Application note ECC/EDC on TDAxx (Rev. B) 13 Jun 2018
User guide TPS65917-Q1 User’s Guide to Power DRA7xx and TDA2x/TDA2Ex (Rev. F) 07 May 2018
User guide TPS65919-Q1 and TPS65917-Q1 User's Guide to Power DRA71x, DRA79x, and TDA2E-17 (Rev. E) 07 May 2018
Application note Sharing VPE Between VISIONSDK and PSDKLA 04 May 2018
Application note TMS320C66x XMC Memory Protection 31 Jan 2018
Application note DSS Bit Exact Output (Rev. A) 12 Jan 2018
Application note Flashing Utility - mflash 09 Jan 2018
Application note Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 07 Nov 2017
Application note A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 03 Nov 2017
Application note DSS BT656 Workaround for TDA2x (Rev. A) 03 Nov 2017
Functional safety information Safety Features on VisionSDK 26 Oct 2017
Application note Optimization of GPU-Based Surround View on TI’s TDA2x SoC 12 Sep 2017
White paper Step into next-gen architectures for multi-camera operations in automobiles 16 Jun 2017
White paper Making Cars Safer Through Technology Innovation (Rev. A) 07 Jun 2017
EVM User's guide TDA2Ex EVM CPU Board User's Guide (Rev. A) 20 Apr 2017
Application note Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 15 Dec 2016
Application note Quad Channel Camera Application for Surround View and CMS Camera Systems (Rev. A) 23 Aug 2016
Application note ADAS Power Management 07 Mar 2016
White paper Multicore SoCs stay a step ahead of SoC FPGAs 23 Feb 2016
User guide Vision Application Board User's Guide 09 Feb 2016
Technical article If seeing is believing… Surround Viewing is experiencing! PDF | HTML 26 Oct 2015
White paper Surround view camera systems for ADAS (Rev. A) 20 Oct 2015
Product overview TDA2Eco ADAS System-on-chip Family 12 Oct 2015
Application note Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 13 Aug 2014
White paper TI Vision SDK, Optimized Vision Libraries for ADAS Systems 14 Apr 2014
White paper TI Gives Sight to Vision-Enabled Automotive Technologies 16 Oct 2013

Design & development

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Information included:
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