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TPS3850

ACTIVE

Precision window supervisor for OV & UV monitoring with window watchdog timer & programmable delay

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Data sheet

TPS3850

ACTIVE
Data sheet Order now

Product details

Number of supplies monitored 1 Threshold voltage 1 (typ) (V) 0.372, 0.428, 1.116, 1.152, 1.248, 1.284, 1.674, 1.728, 1.872, 1.926, 2.79, 2.88, 3.069, 3.12, 3.168, 3.21, 3.432, 3.531, 4.65, 4.8, 5.2 Features Reset time delay, Separate VDD & sense, Timeout watchdog, Undervoltage and overvoltage monitor, Watchdog disable, Watchdog timer, Window watchdog Reset threshold accuracy (%) 0.8 Iq (typ) (mA) 0.01 Output driver type/reset output Active-low, Open-drain Time delay (ms) 10, 200 Supply voltage (min) (V) 1.6 Supply voltage (max) (V) 6.5 Rating Catalog Watchdog timer WDI (s) Programmable Operating temperature range (°C) -40 to 125
Number of supplies monitored 1 Threshold voltage 1 (typ) (V) 0.372, 0.428, 1.116, 1.152, 1.248, 1.284, 1.674, 1.728, 1.872, 1.926, 2.79, 2.88, 3.069, 3.12, 3.168, 3.21, 3.432, 3.531, 4.65, 4.8, 5.2 Features Reset time delay, Separate VDD & sense, Timeout watchdog, Undervoltage and overvoltage monitor, Watchdog disable, Watchdog timer, Window watchdog Reset threshold accuracy (%) 0.8 Iq (typ) (mA) 0.01 Output driver type/reset output Active-low, Open-drain Time delay (ms) 10, 200 Supply voltage (min) (V) 1.6 Supply voltage (max) (V) 6.5 Rating Catalog Watchdog timer WDI (s) Programmable Operating temperature range (°C) -40 to 125
VSON (DRC) 10 9 mm² 3 x 3
  • Input voltage range: VDD = 1.6 V to 6.5 V
  • 0.8% Voltage threshold accuracy
  • Low supply current: IDD = 10 µA (typical)
  • User-programmable watchdog timeout
  • User-programmable reset delay
  • Factory-programmed precision watchdog and reset timers
  • Open-drain outputs
  • Precision over- and undervoltage monitoring:
    • Supports common rails from 0.9 V to 5.0 V
    • ±4% and ±7% Fault windows available
    • 0.5% Hysteresis
  • Watchdog disable feature
  • Available in a small 3-mm × 3-mm, 10-Pin VSON package
  • Junction operating temperature range: –40°C to +125°C
  • Input voltage range: VDD = 1.6 V to 6.5 V
  • 0.8% Voltage threshold accuracy
  • Low supply current: IDD = 10 µA (typical)
  • User-programmable watchdog timeout
  • User-programmable reset delay
  • Factory-programmed precision watchdog and reset timers
  • Open-drain outputs
  • Precision over- and undervoltage monitoring:
    • Supports common rails from 0.9 V to 5.0 V
    • ±4% and ±7% Fault windows available
    • 0.5% Hysteresis
  • Watchdog disable feature
  • Available in a small 3-mm × 3-mm, 10-Pin VSON package
  • Junction operating temperature range: –40°C to +125°C

The TPS3850 combines a precision voltage supervisor with a programmable window watchdog timer. The TPS3850 window comparator achieves 0.8% accuracy (–40°C to +125°C) for both overvoltage (VIT+(OV)) and undervoltage (VIT–(UV)) thresholds on the SENSE pin. The TPS3850 also includes accurate hysteresis on both thresholds, making the device ideal for use with tight tolerance systems. The supervisor RESET delay can be set by factory-programmed default delay settings, or programmed by an external capacitor. The factory-programmed RESET delay features a 9.5% accuracy, high-precision delay timing.

The TPS3850 includes a programmable window watchdog timer for a wide variety of applications. The dedicated watchdog output ( WDO) enables increased resolution to help determine the nature of fault conditions. The window watchdog timeouts can be set by factory-programmed default delay settings, or programmed by an external capacitor. The watchdog can be disabled via logic pins to avoid undesired watchdog timeouts during the development process.

The TPS3850 is available in a small 3.00-mm × 3.00-mm, 10-pin VSON package.

The TPS3850 combines a precision voltage supervisor with a programmable window watchdog timer. The TPS3850 window comparator achieves 0.8% accuracy (–40°C to +125°C) for both overvoltage (VIT+(OV)) and undervoltage (VIT–(UV)) thresholds on the SENSE pin. The TPS3850 also includes accurate hysteresis on both thresholds, making the device ideal for use with tight tolerance systems. The supervisor RESET delay can be set by factory-programmed default delay settings, or programmed by an external capacitor. The factory-programmed RESET delay features a 9.5% accuracy, high-precision delay timing.

The TPS3850 includes a programmable window watchdog timer for a wide variety of applications. The dedicated watchdog output ( WDO) enables increased resolution to help determine the nature of fault conditions. The window watchdog timeouts can be set by factory-programmed default delay settings, or programmed by an external capacitor. The watchdog can be disabled via logic pins to avoid undesired watchdog timeouts during the development process.

The TPS3850 is available in a small 3.00-mm × 3.00-mm, 10-pin VSON package.
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Technical documentation

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Type Title Date
* Data sheet TPS3850 Precision Voltage Supervisor with Programmable Window Watchdog Timer datasheet (Rev. B) PDF | HTML 09 Sep 2021
Application note Voltage Supervisors (Reset ICs): Frequently Asked Questions (FAQs) (Rev. A) 17 Mar 2020
E-book Voltage Supervisor and Reset ICs: Tips, Tricks and Basics 28 Jun 2019
Application note Comparing Voltage and Processor Monitoring Solutions 05 Apr 2019
Application note How Comparator Topology Influences Propagation Delay 05 Apr 2017
Technical article Exploring watchdog timer applications PDF | HTML 02 Feb 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS3850EVM-781 — TPS3850 high-accuracy supervisor with window watchdog timer evaluation module

The TPS3850EVM-781 evaluation module (EVM) is designed for a typical configuration to evaluate the operation and performance of the TPS3850 low-quiescent current (Iq), 0.8% accurate supervisor with integrated watchdog timer.
User guide: PDF
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Simulation model

TPS3850 PSpice Transient Model (Rev. A)

SBVM649A.ZIP (67 KB) - PSpice Model
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Simulation model

TPS3850 Unencrypted PSpice Transient Model (Rev. A)

SBVM648A.ZIP (9 KB) - PSpice Model
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Reference designs

TIDA-01589 — High fidelity, near-field two-way audio reference design with noise reduction and echo cancellation

Man machine interaction requires an acoustic interface for providing full duplex hands-free communication. In hands-free mode, part of the far-end or near-end audio signal from the speaker is coupled to the microphones. Furthermore, in noisy environments the microphones also capture ambient noise (...)
Design guide: PDF
Schematic: PDF
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