PMP10395

18-60VDCin, 6V/31A Active Clamp Forward Reference Design

PMP10395

Design files

Overview

This reference design generates a 6V/31A output from a wide range 18V to 60V DC telecom input.  The UCC2897A controls an active clamp forward converter power stage.  The low gate charge and low RDSon of the CSD18540Q5B, implemented as self-driven synchronous rectifiers, allow this design to achieve a max load efficiency over 94%.  The compact UCC27511 drivers simplify the gate drive circuitry for the synchronous rectifiers.

Features
  • High Efficiency (over 95%)
  • Low profile, less than 0.5 inches (12.5mm) max component height
  • Self-driven synchronous rectifiers reduce drive complexity
Output voltage options PMP10395.1
Vin (Min) (V) 18
Vin (Max) (V) 60
Vout (Nom) (V) 6
Iout (Max) (A) 31
Output Power (W) 186
Isolated/Non-Isolated Isolated
Input Type DC
Topology Forward- Active Clamp^Forward- Synchronous
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDU597.PDF (4559 KB)

Test results for the reference design, including efficiency graphs, test prerequisites and more

TIDRBA9.PDF (88 KB)

Detailed overview of design layout for component placement

TIDRBA8.PDF (85 KB)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRBB0.PDF (338 KB)

PCB layer plot file used for generating PCB design layout

TIDRBA7.PDF (186 KB)

Detailed schematic diagram for design layout and components

Products

Includes TI products in the design and potential alternatives.

MOSFETs

CSD18540Q5B60-V, N channel NexFET™ power MOSFET, single SON 5 mm x 6 mm, 2.2 mOhm

Data sheet: PDF | HTML
AC/DC & DC/DC controllers (external FET)

UCC2897A110-V active clamp current mode PWM controller with P-channel clamp FET and line OV protection

Data sheet: PDF | HTML
Low-side drivers

UCC275114-A/8-A single-channel gate driver with 5-V UVLO, split outputs, and 13-ns Prop delay

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Test report PMP10395 Test Results Oct 14, 2014

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