The PMP10600.1 reference design provides all the power supply rails necessary to power Xilinx® Zynq® 7000 series (XC7Z015) FPGA. This design uses several LMZ3 series modules, LDOs, and a DDR termination regulator. It also features one LM3880 for power up and power down sequencing. This design uses a 12V input.
| Output voltage options | PMP10600.1 | PMP10600.2 |
|---|---|---|
| Vin (Min) (V) | 10.8 | 10.8 |
| Vin (Max) (V) | 13.2 | 13.2 |
| Vout (Nom) (V) | 1 | 1.8 |
| Iout (Max) (A) | 3 | 1.3 |
| Output Power (W) | 3 | 2.34 |
| Isolated/Non-Isolated | Non-Isolated | Non-Isolated |
| Input Type | DC | DC |
| Topology | Buck- Integrated Switch | Buck- Integrated Switch |
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Download ready-to-use system files to speed your design process.
Test results for the reference design, including efficiency graphs, test prerequisites and more
Complete listing of design components, reference designators, and manufacturers/part numbers
Design file that contains information on physical board layer of design PCB
Detailed schematic diagram for design layout and components
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Test report | PMP10600 Test Results | Jan 14, 2015 |
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