TIDA-00153

JESD204B Link Latency Design Using a High Speed ADC

TIDA-00153

Design files

Overview

JESD204B links are the latest trend in data-converter digital interfaces. These links take advantage of high-speed serial-digital technology to offer many compelling benefits including improved channel densities. This reference design addresses one of the challenges of adopting the new interface: understanding and designing the link latency. An example achieves deterministic latency and determines the link latency of a system containing the Texas Instruments LM97937 ADC and Xilinx Kintex 7 FPGA.

Features
  • Guarantee deterministic latency across the JESD204B link
  • Understand the tradeoff between link latency and tolerance to link delay variation
  • Use a formulaic and procedure-based approach to design the link latency
  • Implement a JESD204B link using Texas Instruments' ADC16DX370 or LM97937 ADC and a Xilinx Kintex 7 FPGA
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDU171.PDF (125 K)

Reference design overview and verified performance test data

TIDU229.PDF (392 K)

Test results for the reference design, including efficiency graphs, test prerequisites and more

TIDR411.PDF (162 K)

Detailed schematic diagram for design layout and components

TIDR412.PDF (75 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDC288.ZIP (706 K)

Design file that contains information on physical board layer of design PCB

Products

Includes TI products in the design and potential alternatives.

Clock jitter cleaners

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADC16DX370Dual-Channel, 16-Bit, 370-MSPS Analog-to-Digital Converter (ADC)

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

LP3878-ADJ800-mA, 16-V, adjustable low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

LP5900150-mA, low-noise, low-IQ, low-dropout voltage regulator with enable

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide JESD204B Link Latency Using a High-Speed ADC and FPGA Design Guide Feb. 18, 2014
Test report TIDA-00153 Test Results Feb. 19, 2014

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