JESD204 technology is a standardized serial interface between data converters (ADCs and DACs) and logic devices (FPGAs or ASICs) which uses encoding for SerDes synchronization, clock recovery and DC balance. Our JESD204-compliant products and designs help you significantly improve the performance of high-density systems across a variety of application areas. We provide devices that support JESD204A, JESD204B and JESD204C.
Featured JESD204 design resources
Utilize our license-free JESD204 IP to accelerate your system design connecting FPGAs to TI high-speed data converters.
This white paper explains the differences between JESD204B and JESD204C standards and the impact those changes have on engineers working on high-speed data converter board designs.
|Application note||Extending JESD204B link distance on low-cost substrates|
|Application note||System design considerations when upgrading from JESD204B to JESD204C|
|Training||JESD204B video blog series|
|Training||Three-part JESD204B training series|
|Training||Timing is everything: JESD204B subclass 1 clocking timing requirements|
|White paper||Ready to make the jump to JESD204B?|
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