Clock jitter cleaners & synchronizers – Design & development
Featured evaluation modules
Evaluation module for our ultra-low noise and low-power JESD204B-compliant dual-loop jitter cleaner
Featured reference designs
Featured tools & software
Use our TICSPRO-SW software to program the evaluation modules (EVMs) for our PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
Create and compare multi-chip, system-level clock trees to meet your design requirements.