High-speed ADCs (>10MSPS)
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JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Direct RF-sampling radar receiver for L-, S-, C- and X-band reference design
This reference design uses the ADC12DJ3200 evaluation module (EVM) to demonstrate a direct RF-sampling receiver for a radar operating in HF, VHF, UHF, L-, S-, C- and part of X-band. The wide analog-input bandwidth and high-sampling rate (6.4 GSPS) of the analog-to-digital converter (ADC) provides (...)
1-GHz Signal Bandwidth RF Sampling Receiver Reference Design
New products
Single-channel, 14-bit, 25-MSPS, low-noise, ultra-low-power and low-latency ADC
Single-channel, 14-bit, 10-MSPS, low-noise, ultra-low-power and low-latency ADC
Dual-channel, 16-bit, 25-MSPS, low-noise, ultra-low-power analog-to-digital converter (ADC)
Dual-channel, 18-bit, 25-MSPS, low-noise, ultra-low-power analog-to-digital converter (ADC)
Dual-channel, 12-bit, 1.6-GSPS ADC with JESD204C interface and integrated sample clock generator
Single-channel, 12-bit, 800-MSPS analog-to-digital converter (ADC) with JESD204C interface