An internal PLL with integrated VCO, called the converter PLL (C-PLL), is available for the high-speed sampling clock generation from a low-frequency reference signal to simplify system clocking architectures and to avoid routing of high speed clocks around the circuit board. The C-PLL architecture is shown in Figure 8-6. The PLL is enabled by setting the PLL_EN pin high.
The PLL takes a low-frequency reference clock from the CLK± pins if the PLLREF_SE pin is set low or the SE_CLK pin if the PLLREF_SE pin is set high. The reference clock is applied directly to the phase-frequency detector (PFD). The PFD compares the reference clock phase to the phase of the clock divided-down from the VCO. Therefore, the VCO frequency (fVCO) divided by all of the dividers in the path (V, P, N) must be equal to the reference clock frequency (fREF). The sampling frequency (fS) is then the reference frequency times the N divider or the VCO frequency divided by the V and P dividers. The equations governing the PLL operation are given by Equation 2 and Equation 3.
Equation 4 can be used to calculate the product of the V and P dividers (V × P). Simply choose V and P such that their product equals the calculated product. Equation 5 can be used to calculate the N divider based on the desired sampling rate and reference frequency.
The VCO in the device has a limited tuning range which limits the ADC sampling rates that can be generated by the PLL. The available VCO divisors (product of P and V) and resulting sampling rates are provided in Table 8-4. Only the sampling rates in Table 8-4 are available in the device when the PLL is enabled. If the desired sampling rate is not supported by the PLL then the PLL must be disabled and the desired sampling clock provided to the CLK± pins.
|VCO Divisor (P × V)||Minimum ADC Core Sampling Rate||Maximum ADC Core Sampling Rate|
|6||1200 MSPS||1300 MSPS|
|8||900 MSPS||1025 MSPS|
|10||720 MSPS||820 MSPS|
|12||600 MSPS||683 MSPS|
|16||500 MSPS||513 MSPS|
The C-PLL should be held in reset before changing any of the C-PLL settings by setting register CPLL_RESET to 1 (address = 0x5C CPLL_RESET). The C-PLL dividers can be programmed using registers PLL_P_DIV (address = 0x3D CPLL_FBDIV1), PLL_V_DIV (address = 0x03D CPLL_FBDIV1) and PLL_N_DIV (address = 0x3E CPLL_FBDIV2). After programming the dividers the VCO calibration should be run by first setting register VCO_CAL_EN to 1 (address = 0x5D VCO_CAL_CNTL). The VCO calibration is run when register CPLL_RESET (address = 0x5C CPLL_RESET) is set to 0 to take the C-PLL out of reset. Calibration is finished and the C-PLL is locked when register VCO_CAL_DONE (address = 0x5E VCO_CAL_STATUS) returns 1 and register CPLL_LOCKED (address = 0x208 JESD_STATUS) is 1.
The C-PLL includes noise suppression options for the VA11Q and VCLK11 that reduce the sampling jitter and reference clock input spur at the expense of approximately 20mA of current each. The control bits are found in the CLK_CTRL2 register (address = 0x2B CLK_CTRL2).