SBASAG1 Data sheet

SBASAG1 October 2021 ADC09DJ800 , ADC09QJ800 , ADC09SJ800

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Orderable Information

8.5.7 SPI_Register_Map Registers

Table 8-56 lists the SPI_Register_Map registers. All register offset addresses not listed in Table 8-56 should be considered as reserved locations and the register contents should not be modified.

Table 8-56 SPI_REGISTER_MAP Registers

Address	Acronym	Register Name	Section
0x0	CONFIG_A	Configuration A (default: 0x30)	Go
0x2	DEVICE_CONFIG	Device Configuration (default: 0x00)	Go
0xC	VENDOR_ID	Vendor Identification (Default = 0x0451)	Go
0x10	USR0	User SPI Configuration (Default: 0x00)	Go
0x29	CLK_CTRL0	Clock Control 0 (default: 0x80)	Go
0x2A	CLK_CTRL1	Clock Control 1 (default: 0x00)	Go
0x2B	CLK_CTRL2	Clock Control 2 (default: 0x10)	Go
0x2C	SYSREF_POS	SYSREF Capture Position (read-only status)	Go
0x30	FS_RANGE	FS_RANGE (default: 0xA000)	Go
0x37	LOW_POWER1	Low Power Mode 1 (default: 0x4B)	Go
0x3B	TMSTP_CTRL	TIMESTAMP (TMSTP) Control (default: 0x00)	Go
0x3C	PLLREFO_CTRL	PLL Reference Output Control (default: 0x01)	Go
0x3D	CPLL_FBDIV1	C-PLL Feedback Divider V and P (default: 0x00)	Go
0x3E	CPLL_FBDIV2	C-PLL Feedback Divider N (default: 0x20)	Go
0x3F	CPLL_VCOCTRL1	C-PLL Feedback Divider N (default: 0x4F)	Go
0x48	SER_PE	Serializer Pre-Emphasis Control (default: 0x00)	Go
0x57	TRIGOUT_CTRL	TRIGOUT Output Control (default: 0x00)	Go
0x58	CPLL_OVR	C-PLL Pin Override (default: 0x00)	Go
0x59	VCO_FREQ_TRIM	C-PLL VCO Frequency Trim (default: undefined)	Go
0x5C	CPLL_RESET	C-PLL / VCO Calibration Reset (default: 0x00)	Go
0x5D	VCO_CAL_CTRL	VCO Calibration Control (default: 0x40)	Go
0x5E	VCO_CAL_STATUS	VCO Calibration Status (read-only) (default: undefined)	Go
0x61	CAL_EN	Calibration Enable (Default: 0x01)	Go
0x62	CAL_CFG0	Calibration Configuration 0 (Default: 0x01)	Go
0x65	CAL_CFG1	Calibration Configuration 1 (Default: 0x01)	Go
0x68	CAL_AVG	Calibration Averaging (default: 0x61)	Go
0x6A	CAL_STATUS	Calibration Status (default: undefined) (read-only)	Go
0x6B	CAL_PIN_CFG	Calibration Pin Configuration (default: 0x00)	Go
0x6C	CAL_SOFT_TRIG	Calibration Software Trigger (default: 0x01)	Go
0x6E	CAL_LP	Low-Power Background Calibration (default: 0x88)	Go
0x7A	GAIN_TRIM	Gain DAC Trim (default from Fuse ROM)	Go
0x7C	BG_TRIM	Band-Gap Trim (default from Fuse ROM)	Go
0x7E	RTRIM_A	Resistor Trim for INA (default from Fuse ROM)	Go
0x7F	RTRIM_B	Resistor Trim for INB (default from Fuse ROM)	Go
0x80	RTRIM_C	Resistor Trim for INC (default from Fuse ROM)	Go
0x81	RTRIM_D	Resistor Trim for IND (default from Fuse ROM)	Go
0x9A	ADC_SRC_DLY	ADC Source Delay for Calibration	Section 8.5.7.37
0x9B	MUX_SEL_DLY	MUX selection Delay for Calibration	Section 8.5.7.38
0x9D	ADC_DITH	ADC Dither Control (default from Fuse ROM)	Go
0x160	LSB_CTRL	LSB Control Bit Output (default: 0x00)	Go
0x200	JESD_EN	JESD204C Subsystem Enable (default: 0x01)	Go
0x201	JMODE	JESD204C Mode (default: 0x00)	Go
0x202	KM1	JESD204C K Parameter (minus 1) (default: 0x1F)	Go
0x203	JSYNC_N	JESD204C Manual Sync Request (default: 0x01)	Go
0x204	JCTRL	JESD204C Control (default: 0x03)	Go
0x205	JTEST	JESD204C Test Control (default: 0x00)	Go
0x206	DID	JESD204C DID Parameter (default: 0x00)	Go
0x207	FCHAR	JESD204C Frame Character (default: 0x00)	Go
0x208	JESD_STATUS	JESD204C / System Status Register	Go
0x209	CH_EN	JESD204C Channel Enable (default: 0x03)	Go
0x20F	SHMODE	JESD204C Sync Word Mode (default: 0x00)	Go
0x210	SYNC_THRESH	JESD204C SYNC~ Threshold (default: 0x03)	Go
0x211	OVR_TH	Over-range Threshold (default: 0xF2)	Go
0x213	OVR_CFG	Over-range Enable / Hold Off (default: 0x07)	Go
0x270	INIT_STATUS	Initialization Status (read-only)	Go
0x29A	LOW_POWER2	Low Power Mode 2 (default: 0x0F)	Go
0x29B	LOW_POWER3	Low Power Mode 3 (default: 0x04)	Go
0x29C	LOW_POWER4	Low Power Mode 4 (default: 0x1B)	Go
0x2C0	ALARM	Alarm Interrupt (read-only)	Go
0x2C1	ALM_STATUS	Alarm Status (default: 0x3F, write to clear)	Go
0x2C2	ALM_MASK	Alarm Mask Register (default: 0x3F)	Go
0x2C4	FIFO_LANE_ALM	FIFO Overflow/Underflow Alarm (default: 0xFF)	Go
0x330	OFS0	Offset Adjustment for ADC0 (default from Fuse ROM)	Go
0x332	OFS1	Offset Adjustment for ADC1 (default from Fuse ROM)	Go
0x334	OFS2A	Offset Adjustment for ADC2 (INA±) (default from Fuse ROM)	Go
0x336	OFS2B	Offset Adjustment for ADC2 (INB±) (default from Fuse ROM)	Go
0x338	OFS3C	Offset Adjustment for ADC3 (INC±) (default from Fuse ROM)	Go
0x33A	OFS3D	Offset Adjustment for ADC3 (IND±) (default from Fuse ROM)	Go
0x33C	OFS4	Offset Adjustment for ADC4 (default from Fuse ROM)	Go
0x33E	OFS5	Offset Adjustment for ADC5 (default from Fuse ROM)	Go
0x360	GAIN0	Fine Gain Adjust for ADC0 (default from Fuse ROM)	Go
0x361	GAIN1	Fine Gain Adjust for ADC1 (default from Fuse ROM)	Go
0x362	GAIN2A	Fine Gain Adjust for ADC2 (INA±) (default from Fuse ROM)	Go
0x363	GAIN2B	Fine Gain Adjust for ADC2 (INB±) (default from Fuse ROM)	Go
0x364	GAIN3C	Fine Gain Adjust for ADC3 (INC±) (default from Fuse ROM)	Go
0x365	GAIN3D	Fine Gain Adjust for ADC3 (IND±) (default from Fuse ROM)	Go
0x366	GAIN4	Fine Gain Adjust for ADC4 (default from Fuse ROM)	Go
0x367	GAIN5	Fine Gain Adjust for ADC5 (default from Fuse ROM)	Go

Complex bit access types are encoded to fit into small table cells. Table 8-57 shows the codes that are used for access types in this section.

Table 8-57 SPI_Register_Map Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value
Register Array Variables
i,j,k,l,m,n		When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y		When this variable is used in a register name, an offset, or an address it refers to the value of a register array.

8.5.7.1 CONFIG_A Register (Address = 0x0) [reset = 0x30]

CONFIG_A is shown in Figure 8-20 and described in Table 8-58.

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Configuration A (default: 0x30)

Figure 8-20 CONFIG_A Register

7	6	5	4	3	2	1	0
SOFT_RESET	RESERVED	ASCEND	SDO_ACTIVE	RESERVED
R/W-0x0	R/W-0x0	R/W-0x1	R-0x1	R/W-0x0

Table 8-58 CONFIG_A Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SOFT_RESET	R/W	0x0	Setting this bit causes a full reset of the chip and all SPI registers (including CONFIG_A). This bit is self-clearing. After writing this bit, the part may take up to 750ns to reset. During this time, do not perform any SPI transactions.
6	RESERVED	R/W	0x0	Must write default value.
5	ASCEND	R/W	0x1	0 : Address is decremented during streaming reads/writes 1 : Address is incremented during streaming reads/writes (default)
4	SDO_ACTIVE	R	0x1	Always returns 1. Always use SDO for SPI reads. No SDIO mode supported.
3:0	RESERVED	R/W	0x0

8.5.7.2 DEVICE_CONFIG Register (Address = 0x2) [reset = 0x00]

DEVICE_CONFIG is shown in Figure 8-21 and described in Table 8-59.

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Device Configuration (default: 0x00)

Figure 8-21 DEVICE_CONFIG Register

7	6	5	4	3	2	1	0
RESERVED						MODE
R/W-0x0						R/W-0x0

Table 8-59 DEVICE_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:2	RESERVED	R/W	0x0	Must write default value.
1:0	MODE	R/W	0x0	0 : Normal operation (default) 1 : Reserved 2 : Reserved 3 : Power down (full device)

8.5.7.3 VENDOR_ID Register (Address = 0xC) [reset = 0x0]

VENDOR_ID is shown in Figure 8-22 and described in Table 8-60.

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Vendor Identification (Default = 0x0451)

Figure 8-22 VENDOR_ID Register

15	14	13	12	11	10	9	8
VENDOR_ID
R-0x0

7	6	5	4	3	2	1	0
VENDOR_ID
R-0x0

Table 8-60 VENDOR_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	VENDOR_ID	R	0x0	Always returns 0x0451 (Vendor ID for Texas Instruments)

8.5.7.4 USR0 Register (Address = 0x10) [reset = 0x00]

USR0 is shown in Figure 8-23 and described in Table 8-61.

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User SPI Configuration (Default: 0x00)

Figure 8-23 USR0 Register

7	6	5	4	3	2	1	0
RESERVED							ADDR_HOLD
R/W-0x0							R/W-0x0

Table 8-61 USR0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R/W	0x0	Must write default value.
0	ADDR_HOLD	R/W	0x0	0 : Use ASCEND register to select address ascend/descend mode (default) 1 : Address stays constant throughout streaming operation; useful for reading and writing calibration vector information at the CAL_DATA register

8.5.7.5 CLK_CTRL0 Register (Address = 0x29) [reset = 0x80]

CLK_CTRL0 is shown in Figure 8-24 and described in Table 8-62.

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Clock Control 0 (default: 0x80)

Figure 8-24 CLK_CTRL0 Register

7	6	5	4	3	2	1	0
RESERVED	SYSREF_PROC_EN	SYSREF_RECV_EN	SYSREF_ZOOM	SYSREF_SEL
R/W-0x1	R/W-0x0	R/W-0x0	R/W-0x0	R/W-0x0

Table 8-62 CLK_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0x1	Must write default value.
6	SYSREF_PROC_EN	R/W	0x0	This bit enables the SYSREF processor, which allows the device to process SYSREF events (default: disabled). SYSREF_RECV_EN must be set before setting SYSREF_PROC_EN.
5	SYSREF_RECV_EN	R/W	0x0	Set this bit to enable the SYSREF receiver circuit (default: disabled)
4	SYSREF_ZOOM	R/W	0x0	Set this bit to zoom in the SYSREF windowing status and delays (impacts SYSERF_POS and SYSREF_SEL). When set, the delays used in the SYSREF windowing feature (reported in the SYSREF_POS register) become smaller. Use SYSREF_ZOOM for high clock rates, specifically when multiple SYSREF valid windows are encountered in the SYSREF_POS register; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section.
3:0	SYSREF_SEL	R/W	0x0	Set this field to select which SYSREF delay to use. Set this field based on the results returned by SYSREF_POS; see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section.

8.5.7.6 CLK_CTRL1 Register (Address = 0x2A) [reset = 0x00]

CLK_CTRL1 is shown in Figure 8-25 and described in Table 8-63.

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Clock Control 1 (default: 0x00)

Figure 8-25 CLK_CTRL1 Register

7	6	5	4	3	2	1	0
RESERVED					DEVCLK_LVPECL_EN	SYSREF_LVPECL_EN	SYSREF_INVERTED
R/W-0x0					R/W-0x0	R/W-0x0	R/W-0x0

Table 8-63 CLK_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:3	RESERVED	R/W	0x0	Must write default value.
2	DEVCLK_LVPECL_EN	R/W	0x0	Activate low voltage PECL mode for DEVCLK. The internal termination for each input pin (CLK+ and CLK–) becomes a 50-Ω resistor to ground. There is no input common-mode self-biasing for CLK± when DEVCLK_LVPECL_EN is set to 1.
1	SYSREF_LVPECL_EN	R/W	0x0	Activate low voltage PECL mode for SYSREF. The internal termination for each input pin (SYSREF+ and SYSREF–) becomes a 50-Ω resistor to ground. There is no input common-mode self-biasing for SYSREF± when SYSREF_LVPECL_EN is set to 1.
0	SYSREF_INVERTED	R/W	0x0	This bit inverts the SYSREF signal used for alignment.

8.5.7.7 CLK_CTRL2 Register (Address = 0x2B) [reset = 0x10]

CLK_CTRL2 is shown in Figure 8-26 and described in Table 8-64.

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Clock Control 1 (default: 0x10)

Figure 8-26 CLK_CTRL2 Register

7	6	5	4	3	2	1	0
RESERVED					VA11Q_NOISESUPPR_EN	RESERVED	VCLK11_NOISESUPPR_EN
R/W-0x1					R/W-0x0	R/W-0x0	R/W-0x0

Table 8-64 CLK_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:3	RESERVED	R/W	0x0	Must write default value.
2	VA11Q_NOISESUPPR_EN	R/W	0x0	When set, noise on VA11Q is suppressed while drawing ~ 20mA of current. This will reduce sampling jitter and reduce the reference clock spur in C-PLL modes and SYSREF spurs.
1	RESERVED	R/W	0x0	Must write default value.
0	VCLK11_NOISESUPPR_EN	R/W	0x0	When set, noise on VCLK11 is suppressed while drawing ~ 20mA of current. This will reduce sampling jitter and reduce the reference clock spur in C-PLL modes and SYSREF spurs.

8.5.7.8 SYSREF_POS Register (Address = 0x2C) [reset = 0x0]

SYSREF_POS is shown in Figure 8-27 and described in Table 8-65.

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SYSREF Capture Position (read-only status)

Figure 8-27 SYSREF_POS Register

23	22	21	20	19	18	17	16
SYSREF_POS
R-0x0

15	14	13	12	11	10	9	8
SYSREF_POS
R-0x0

7	6	5	4	3	2	1	0
SYSREF_POS
R-0x0

Table 8-65 SYSREF_POS Register Field Descriptions

Bit	Field	Type	Reset	Description
23:0	SYSREF_POS	R	0x0	Returns a 24-bit status value that indicates the position of the SYSREF edge with respect to CLK±. Use this to program SYSREF_SEL.

8.5.7.9 FS_RANGE Register (Address = 0x30) [reset = 0xA000]

FS_RANGE is shown in Figure 8-28 and described in Table 8-66.

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FS_RANGE (default: 0xA000)

Figure 8-28 FS_RANGE Register

15	14	13	12	11	10	9	8
FS_RANGE
R/W-0xA000

7	6	5	4	3	2	1	0
FS_RANGE
R/W-0xA000

Table 8-66 FS_RANGE Register Field Descriptions

Bit	Field	Type	Reset	Description
15:0	FS_RANGE	R/W	0xA000	These bits enable adjustment of the analog full-scale range for all channels. 0x0000: Settings below 0x2000 result in degraded performance 0x2000: 500 mVPP - Recommended minimum setting 0xA000: 800 mVPP (default) 0xFFFF: 1000 mVPP - Maximum setting, highest SNR

8.5.7.10 LOW_POWER1 Register (Address = 0x37) [reset = 0x4B]

LOW_POWER1 is shown in Figure 8-29 and described in Table 8-67.

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Low Power Mode 1 (default: 0x4B)

Figure 8-29 LOW_POWER1 Register

7	6	5	4	3	2	1	0
LOW_POW_MODE1
R/W-0x4B

Table 8-67 LOW_POWER1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	LOW_POW_MODE1	R/W	0x4B	Set this register along with LOW_POWER2, LOW_POWER3 and LOW_POWER4 to enable Low Power Mode. All registers must be set together. Calibration must be performed after changing the operating mode: 0x46 : Low Power Mode 0x4B : High Performance Mode (default) All other values are RESERVED Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this register.

8.5.7.11 TMSTP_CTRL Register (Address = 0x3B) [reset = 0x00]

TMSTP_CTRL is shown in Figure 8-30 and described in Table 8-68.

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TIMESTAMP (TMSTP) Control (default: 0x00)

Figure 8-30 TMSTP_CTRL Register

7	6	5	4	3	2	1	0
RESERVED						TMSTP_LVPECL_EN	TMSTP_RECV_EN
R/W-0x0						R/W-0x0	R/W-0x0

Table 8-68 TMSTP_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:2	RESERVED	R/W	0x0	Must write default value.
1	TMSTP_LVPECL_EN	R/W	0x0	When set, activates the low voltage PECL mode for the differential TMSTP± input. The internal termination for each input pin (TMSTP+ and TMSTP–) becomes a 50-Ω resistor to ground. There is no input common-mode self-biasing for TMSTP± when TMSTP_LVPECL_EN is set to 1.
0	TMSTP_RECV_EN	R/W	0x0	Enables the differential differential TMSTP± input.

8.5.7.12 PLLREFO_CTRL Register (Address = 0x3C) [reset = 0x01]

PLLREFO_CTRL is shown in Figure 8-31 and described in Table 8-69.

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PLL Reference Output Control (default: 0x01)

Figure 8-31 PLLREFO_CTRL Register

7	6	5	4	3	2	1	0
RESERVED							PLLREFO_EN
R/W-0x0							R/W-0x1

Table 8-69 PLLREFO_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R/W	0x0	Must write default value.
0	PLLREFO_EN	R/W	0x1	When set the reference clock output (PLLREFO±) is enabled whenever the PLL is enabled (PLL_EN=1). This bit defaults to 1 to cause PLLREFO± to enable automatically without SPI writes since PLLREFO± may be used to derive the SPI clock.

8.5.7.13 CPLL_FBDIV1 Register (Address = 0x3D) [reset = 0x00]

CPLL_FBDIV1 is shown in Figure 8-32 and described in Table 8-70.

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C-PLL Feedback Divider V and P (default: 0x00)

Figure 8-32 CPLL_FBDIV1 Register

7	6	5	4	3	2	1	0
RESERVED				PLL_P_DIV		PLL_V_DIV
R/W-0x0				R/W-0x0		R/W-0x0

Table 8-70 CPLL_FBDIV1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R/W	0x0	Must write default value.
3:2	PLL_P_DIV	R/W	0x0	Controls the second feedback divider of C-PLL. The output of this divider is the sampling clock. Set CPLL_RESET=1 before changing PLL_P_DIV. 0 : divide-by-1 (default) 1 : divide-by-2 2 : divide-by-4 3 : RESERVED
1:0	PLL_V_DIV	R/W	0x0	Controls the first feedback divider of C-PLL. The output of this divider feeds the P divider. Set CPLL_RESET=1 before changing PLL_V_DIV. 0 : divide-by-5 (default) 1 : divide-by-4 2 : divide-by-3 3 : RESERVED

8.5.7.14 CPLL_FBDIV2 Register (Address = 0x3E) [reset = 0x20]

CPLL_FBDIV2 is shown in Figure 8-33 and described in Table 8-71.

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C-PLL Feedback Divider N (default: 0x20)

Figure 8-33 CPLL_FBDIV2 Register

7	6	5	4	3	2	1	0
RESERVED		PLL_N_DIV
R/W-0x0		R/W-0x20

Table 8-71 CPLL_FBDIV2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R/W	0x0	Must write default value.
5:0	PLL_N_DIV	R/W	0x20	Controls the third feedback divider of C-PLL (default is divide-by-32). This divider divides the sampling clock to generate the PFD feedback clock. The value of PLL_N_DIV is the divider value. Values from 1 to 63 are supported. Set CPLL_RESET=1 before changing PLL_N_DIV.

8.5.7.15 CPLL_VCOCTRL1 Register (Address = 0x3F) [reset = 0x4F, recommended 0x4A]

CPLL_VCOCTRL1 is shown in Figure 8-34 and described in Table 8-72.

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C-PLL Feedback Divider N (default: 0x4F)

Figure 8-34 CPLL_VCOCTRL1 Register

7	6	5	4	3	2	1	0
RESERVED	VCO_BIAS
R/W-0x0	R/W-0x4F

Table 8-72 CPLL_VCOCTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0x0	Must write default value.
6:0	VCO_BIAS	R/W	0x4F	Sets the bias levels for the C-PLL VCO. Write 0x4A to this field when using the C-PLL. Do not use the default value of 0x4F.

8.5.7.16 SER_PE Register (Address = 0x48) [reset = 0x00]

SER_PE is shown in Figure 8-35 and described in Table 8-73.

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Serializer Pre-Emphasis Control (default: 0x00)

Figure 8-35 SER_PE Register

7	6	5	4	3	2	1	0
RESERVED				SER_PE
R/W-0x0				R/W-0x0

Table 8-73 SER_PE Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R/W	0x0	Must write default value.
3:0	SER_PE	R/W	0x0	Sets the pre-emphasis for the SerDes output lanes. Pre-emphasis can be used to compensate for the high-frequency loss of the PCB trace. This is a global setting that affects all lanes (D[7:0]±).

8.5.7.17 TRIGOUT_CTRL Register (Address = 0x57) [reset = 0x00]

TRIGOUT_CTRL is shown in Figure 8-36 and described in Table 8-74.

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TRIGOUT Output Control (default: 0x00)

Figure 8-36 TRIGOUT_CTRL Register

7	6	5	4	3	2	1	0
TRIGOUT_EN	RESERVED				TRIGOUT
R/W-0x0	R/W-0x0				R/W-0x0

Table 8-74 TRIGOUT_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TRIGOUT_EN	R/W	0x0	0 : TRIGOUT± output buffer/divider is disabled. 1 : TRIGOUT± output buffer/divider is enabled. The RXCLK output can be used to provide a reference clock for the JESD204C receiver. Use the TRIGOUT_MODE field to adjust the output mode.
6:3	RESERVED	R/W	0x0	Must write default value.
2:0	TRIGOUT	R/W	0x0	Set the mode for the TRIGOUT± output. 0 : 16 UI clock (RX_DIV = 16) 1 : 32 UI clock (RX_DIV = 32) 2 : 64 UI clock (RX_DIV = 64) 3 : Resampled timestamp from TMSTP± 4-7 : RESERVED Note 1: Only change TRIGOUT_MODE when TRIGOUT_EN=0. Note 2: When TRIGOUT_MODE is 2 or less, TRIGOUT± is derived from the SerDes block. As a result, the TRIGOUT± output is briefly disrupted any time the serializer is re-initialized.

8.5.7.18 CPLL_OVR Register (Address = 0x58) [reset = 0x00]

CPLL_OVR is shown in Figure 8-37 and described in Table 8-75.

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C-PLL Pin Override (default: 0x00)

Figure 8-37 CPLL_OVR Register

7	6	5	4	3	2	1	0
CPLL_OVR_EN	RESERVED	DIVREF_D_MODE		DIVREF_C_MODE		CPLLREF_SE_OVR_VALUE	CPLL_EN_OVR_VALUE
R/W-0x0	R/W-0x0	R/W-0x0		R/W-0x0		R/W-0x0	R/W-0x0

Table 8-75 CPLL_OVR Register Field Descriptions

Bit	Field	Type	Reset	Description
7	CPLL_OVR_EN	R/W	0x0	Set this bit to ignore the C-PLL configuration pins and use SPI registers instead. 0 : Pin Mode : The C-PLL is controlled by chip pins (PLL_EN, PLLREF_SE, CLKCFG0, CLKCFG1) 1 : SPI Mode : The C-PLL is controlled by SPI registers (CPLLREF_SE_OVR_VALUE, CPLL_EN_OVR_VALUE, DIVREF_C_MODE, DIVREF_D_MODE)
6	RESERVED	R/W	0x0	Must write default value.
5:4	DIVREF_D_MODE	R/W	0x0	When CPLL_OVR_EN=1, this field sets the ORD output function. When CPLL_OVR_EN=0, this field has no effect (CLKCFG0 and CLKCFG1 controls ORD functionality). 0 : Divided reference output is disabled. 1 : Output C-PLL reference clock divided by 1 on ORD. 2 : Output C-PLL reference clock divided by 2 on ORD. 3 : Output C-PLL reference clock divided by 4 on ORD. **Important Note: ORD cannot produce a clock unless ORC is also producing a clock).
3:2	DIVREF_C_MODE	R/W	0x0	When CPLL_OVR_EN=1, this field sets the ORC output function. When CPLL_OVR_EN=0, this field has no effect (CLKCFG0 and CLKCFG1 controls ORC functionality). 0 : Divided reference output is disabled. 1 : Output C-PLL reference clock divided by 1 on ORC. 2 : Output C-PLL reference clock divided by 2 on ORC. 3 : Output C-PLL reference clock divided by 4 on ORC.
1	CPLLREF_SE_OVR_VALUE	R/W	0x0	When CPLL_OVR_EN=1, this bit enables the single-ended C-PLL reference clock input (SE_CLK) when set to 1 instead of the PLLREF_SE pin.
0	CPLL_EN_OVR_VALUE	R/W	0x0	When CPLL_OVR_EN=1, this bit enables the C-PLL when set to 1 instead of the PLL_EN pin.

8.5.7.19 VCO_FREQ_TRIM Register (Address = 0x59) [reset = 0x0]

VCO_FREQ_TRIM is shown in Figure 8-38 and described in Table 8-76.

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C-PLL VCO Frequency Trim (default: undefined)

Figure 8-38 VCO_FREQ_TRIM Register

7	6	5	4	3	2	1	0
RESERVED	VCO_FREQ_TRIM
R/W-0x0	R/W-0x0

Table 8-76 VCO_FREQ_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0x0	Must write default value.
6:0	VCO_FREQ_TRIM	R/W	0x0	Trims C-PLL VCO frequency. This field can be automatically set by the VCO calibration routine (see VCO_CAL_EN). After VCO calibration has been run the value can be read from this field and reprogrammed after future power-up cycles. If VCO calibration is running (VCO_CAL_EN=1 and VCO_CAL_DONE=0), you should not read or write this register since it will interfere with the calibration process.

8.5.7.20 CPLL_RESET Register (Address = 0x5C) [reset = 0x00]

CPLL_RESET is shown in Figure 8-39 and described in Table 8-77.

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C-PLL / VCO Calibration Reset (default: 0x00)

Figure 8-39 CPLL_RESET Register

7	6	5	4	3	2	1	0
RESERVED							CPLL_RESET
R/W-0x0							R/W-0x0

Table 8-77 CPLL_RESET Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R/W	0x0	Must write default value.
0	CPLL_RESET	R/W	0x0	C-PLL / VCO calibration reset. Program CPLL_RESET=1 before programming the C-PLL (PLL_P_DIV, PLL_V_DIV, PLL_N_DIV, VCO_BIAS or VCO_CAL_CTRL). Program CPLL_RESET=0 after programming is completed.

8.5.7.21 VCO_CAL_CTRL Register (Address = 0x5D) [reset = 0x40]

VCO_CAL_CTRL is shown in Figure 8-40 and described in Table 8-78.

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VCO Calibration Control (default: 0x40)

Figure 8-40 VCO_CAL_CTRL Register

7	6	5	4	3	2	1	0
RESERVED	VCO_CAL_STL			RESERVED			VCO_CAL_EN
R/W-0x0	R/W-0x4			R/W-0x0			R/W-0x0

Table 8-78 VCO_CAL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0x0	Must write default value.
6:4	VCO_CAL_STL	R/W	0x4	Program this field to adjust the settling time that the VCO calibration engine gives to the C-PLL each time it changes the VCO frequency trim (VCO_FREQ_TRIM). Larger numbers result in longer settling times.
3:1	RESERVED	R/W	0x0	Must write default value.
0	VCO_CAL_EN	R/W	0x0	Set this bit to enable the VCO calibration engine. The calibration commences once CPLL_RESET is programmed to 0. The calibration will automatically tune VCO_FREQ_TRIM to center the VCO frequency based on the reference frequency and PLL configuration. Note: The VCO_CAL_CTRL register should only be changed when CPLL_RESET=1.

8.5.7.22 VCO_CAL_STATUS Register (Address = 0x5E) [reset = 0x0]

VCO_CAL_STATUS is shown in Figure 8-41 and described in Table 8-79.

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VCO Calibration Status (read-only) (default: undefined)

Figure 8-41 VCO_CAL_STATUS Register

7	6	5	4	3	2	1	0
RESERVED							VCO_CAL_DONE
R-0x0							R-0x0

Table 8-79 VCO_CAL_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R	0x0
0	VCO_CAL_DONE	R	0x0	This bit returns ‘1’ once the VCO calibration engine has completed calibration (or calibration was skipped because VCO_CAL_EN=0). Once the calibration is completed, you can safely read or write the VCO_FREQ_TRIM register (never write VCO_FREQ_TRIM during calibration).

8.5.7.23 CAL_EN Register (Address = 0x61) [reset = 0x01]

CAL_EN is shown in Figure 8-42 and described in Table 8-80.

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Calibration Enable (Default: 0x01)

Figure 8-42 CAL_EN Register

7	6	5	4	3	2	1	0
RESERVED							CAL_EN
R/W-0x0							R/W-0x1

Table 8-80 CAL_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R/W	0x0	Must write default value.
0	CAL_EN	R/W	0x1	Calibration Enable. Set high to run calibration. Set low to hold calibration in reset to program new calibration settings. Clearing CAL_EN also resets the clock dividers that clock the digital block and JESD204C interface. Some calibration registers require clearing CAL_EN before making any changes. All registers with this requirement contain a note in their descriptions. After changing the registers, set CAL_EN to re-run calibration with the new settings. Always set CAL_EN before setting JESD_EN. Always clear JESD_EN before clearing CAL_EN.

8.5.7.24 CAL_CFG0 Register (Address = 0x62) [reset = 0x01]

CAL_CFG0 is shown in Figure 8-43 and described in Table 8-81.

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Calibration Configuration 0 (Default: 0x01)

Figure 8-43 CAL_CFG0 Register

7	6	5	4	3	2	1	0
RESERVED				CAL_BGOS	CAL_OS	CAL_BG	CAL_FG
R/W-0x0				R/W-0x0	R/W-0x0	R/W-0x0	R/W-0x1

Table 8-81 CAL_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R/W	0x0	Must write default value.
3	CAL_BGOS	R/W	0x0	0 : Disable background offset calibration (default) 1 : Enable background offset calibration (requires CAL_BG to be set).
2	CAL_OS	R/W	0x0	0 : Disable foreground offset calibration (default) 1 : Enable foreground offset calibration (requires CAL_FG to be set).
1	CAL_BG	R/W	0x0	0 : Disable background calibration (default) 1 : Enable background calibration
0	CAL_FG	R/W	0x1	0 : Reset calibration values, skip foreground calibration. 1 : Reset calibration values, then run foreground calibration (default).

8.5.7.25 CAL_CFG1 Register (Address = 0x65) [reset = 0x01]

CAL_CFG1 is shown in Figure 8-44 and described in Table 8-82.

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Calibration Configuration 1 (Default: 0x01)

Figure 8-44 CAL_CFG1 Register

7	6	5	4	3	2	1	0
RESERVED					OSREF	RESERVED
R/W-0x0					R/W-0x0	R/W-0x1

Table 8-82 CAL_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:3	RESERVED	R/W	0x0	Must write default value.
2	OSREF	R/W	0x0	Defines which reference is used for offset calibration: 0 : Use mid-code as the reference (calibrate to zero-offset). The analog input signal must have no offset during offset calibration (typically true if AC-coupled). 1 : Use the spare ADC output samples as the reference (calibrates primary ADC offsets to match the spare ADC that stands in for them). The analog input signal can have an offset (e.g. DC-coupled). Only use this mode when CAL_BG=1. Setting OSREF=1 while CAL_BG=0 will produce undefined results.
1:0	RESERVED	R/W	0x1	Must write default value.

8.5.7.26 CAL_AVG Register (Address = 0x68) [reset = 0x61]

CAL_AVG is shown in Figure 8-45 and described in Table 8-83.

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Calibration Averaging (default: 0x61)

Figure 8-45 CAL_AVG Register

7	6	5	4	3	2	1	0
RESERVED	OS_AVG			RESERVED	CAL_AVG
R/W-0x0	R/W-0x6			R/W-0x0	R/W-0x1

Table 8-83 CAL_AVG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0x0	Must write default value.
6:4	OS_AVG	R/W	0x6	Select the amount of averaging used for the offset correction routine. A larger number corresponds to more averaging.
3	RESERVED	R/W	0x0	Must write default value.
2:0	CAL_AVG	R/W	0x1	Select the amount of averaging used for the linearity calibration routine. A larger number corresponds to more averaging.

8.5.7.27 CAL_STATUS Register (Address = 0x6A) [reset = 0x0]

CAL_STATUS is shown in Figure 8-46 and described in Table 8-84.

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Calibration Status (default: undefined) (read-only)

Figure 8-46 CAL_STATUS Register

7	6	5	4	3	2	1	0
RESERVED			CAL_STAT			CAL_STOPPED	FG_DONE
R-0x0			R-0x0			R-0x0	R-0x0

Table 8-84 CAL_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0x0
4:2	CAL_STAT	R	0x0	Calibration status code
1	CAL_STOPPED	R	0x0	This bit returns a 1 when background calibration is successfully stopped at the requested phase. This bit returns a 0 when calibration starts operating again. If background calibration is disabled, this bit is set when foreground calibration is completed or skipped.
0	FG_DONE	R	0x0	This bit is high to indicate that foreground calibration has completed (or was skipped).

8.5.7.28 CAL_PIN_CFG Register (Address = 0x6B) [reset = 0x00]

CAL_PIN_CFG is shown in Figure 8-47 and described in Table 8-85.

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Calibration Pin Configuration (default: 0x00)

Figure 8-47 CAL_PIN_CFG Register

7	6	5	4	3	2	1	0
RESERVED					CAL_STATUS_SEL		CAL_TRIG_EN
R/W-0x0					R/W-0x0		R/W-0x0

Table 8-85 CAL_PIN_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:3	RESERVED	R/W	0x0	Must write default value.
2:1	CAL_STATUS_SEL	R/W	0x0	0 : CALSTAT output matches FG_DONE. 1 : CALSTAT output matches CAL_STOPPED. 2 : CALSTAT output matches ALARM. 3 : CALSTAT output is always low.
0	CAL_TRIG_EN	R/W	0x0	This bit selects the hardware or software trigger source. 0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The CALTRIG input is disabled (ignored). 1 : Use the CALTRIG input for the calibration trigger. The CAL_SOFT_TRIG register is ignored.

8.5.7.29 CAL_SOFT_TRIG Register (Address = 0x6C) [reset = 0x01]

CAL_SOFT_TRIG is shown in Figure 8-48 and described in Table 8-86.

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Calibration Software Trigger (default: 0x01)

Figure 8-48 CAL_SOFT_TRIG Register

7	6	5	4	3	2	1	0
RESERVED							CAL_SOFT_TRIG
R/W-0x0							R/W-0x1

Table 8-86 CAL_SOFT_TRIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R/W	0x0	Must write default value.
0	CAL_SOFT_TRIG	R/W	0x1	CAL_SOFT_TRIG is a software bit to provide the functionality of the CALTRIG input pin when there are no hardware resources to drive CALTRIG. Program CAL_TRIG_EN=0 to use CAL_SOFT_TRIG for the calibration trigger. Note: If no calibration trigger is needed, leave CAL_TRIG_EN=0 and CAL_SOFT_TRIG=1 (trigger set high).

8.5.7.30 CAL_LP Register (Address = 0x6E) [reset = 0x88]

CAL_LP is shown in Figure 8-49 and described in Table 8-87.

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Low-Power Background Calibration (default: 0x88)

Figure 8-49 CAL_LP Register

7	6	5	4	3	2	1	0
LP_SLEEP_DLY			LP_WAKE_DLY		RESERVED	LP_TRIG	LP_EN
R/W-0x4			R/W-0x1		R/W-0x0	R/W-0x0	R/W-0x0

Table 8-87 CAL_LP Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	LP_SLEEP_DLY	R/W	0x4	These bits adjust how long an ADC sleeps before waking for calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values below 4 are not recommended because of limited overall power reduction benefits. 0: Sleep delay = 1,152 × tCLK 1: Sleep delay = 4,194,432 × tCLK 2: Sleep delay = 33,554,560 × tCLK 3: Sleep delay = 268,435,584‬ × tCLK 4: Sleep delay = 2,147,483,776 × tCLK (default, approximately 2.15 seconds with a 1.0-GHz clock) 5: Sleep delay = 17,179,869,312‬× tCLK 6: Sleep delay = 137,438,953,600‬ × tCLK 7: Sleep delay = 1,099,511,627,904‬ × tCLK
4:3	LP_WAKE_DLY	R/W	0x1	These bits adjust how much time is provided for settling before calibrating an ADC after the ADC wakes up (only applies when LP_EN = 1). Values lower than 1 are not recommended because there is insufficient time for the core to stabilize before calibration begins. 0: Wake delay = 1,152 × tCLK 1: Wake delay = 33,554,560 × tCLK (default, approximately 34 ms with a 1.0-GHz clock) 2: Wake delay = 268,435,584 × tCLK 3: Wake delay = 2,147,483,776 × tCLK
2	RESERVED	R/W	0x0	Must write default value.
1	LP_TRIG	R/W	0x0	0 : ADC sleep duration is set by LP_SLEEP_DLY (autonomous mode). 1 : ADCs sleep until awoken by a trigger. An ADC is awoken when the calibration trigger is low. The offline ADC is sleeping when the calibration trigger is high.
0	LP_EN	R/W	0x0	0 : Disable low-power background calibration (default) 1 : Enable low-power background calibration (only applies when CAL_BG=1).

8.5.7.31 GAIN_TRIM Register (Address = 0x7A) [reset = 0x0]

GAIN_TRIM is shown in Figure 8-50 and described in Table 8-88.

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Gain DAC Trim (default from Fuse ROM)

Figure 8-50 GAIN_TRIM Register

7	6	5	4	3	2	1	0
GAIN_TRIM
R/W-0x0

Table 8-88 GAIN_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	GAIN_TRIM	R/W	0x0	This register trims the gain of all ADC cores. FS_RANGE should be used for full-scale range adjustment instead of GAIN_TRIM.

8.5.7.32 BG_TRIM Register (Address = 0x7C) [reset = 0x0]

BG_TRIM is shown in Figure 8-51 and described in Table 8-89.

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Band-Gap Trim (default from Fuse ROM)

Figure 8-51 BG_TRIM Register

7	6	5	4	3	2	1	0
RESERVED				BG_TRIM
R/W-0x0				R/W-0x0

Table 8-89 BG_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R/W	0x0	Must write default value.
3:0	BG_TRIM	R/W	0x0	This register enables trimming of the internal band-gap reference. After reset, the factory trimmed value can be read and adjusted as required.

8.5.7.33 RTRIM_A Register (Address = 0x7E) [reset = 0x0]

RTRIM_A is shown in Figure 8-52 and described in Table 8-90.

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Resistor Trim for INA (default from Fuse ROM)

Figure 8-52 RTRIM_A Register

7	6	5	4	3	2	1	0
RTRIM_A
R/W-0x0

Table 8-90 RTRIM_A Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	RTRIM_A	R/W	0x0	This register controls the INA± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

8.5.7.34 RTRIM_B Register (Address = 0x7F) [reset = 0x0]

RTRIM_B is shown in Figure 8-53 and described in Table 8-91.

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Resistor Trim for INB (default from Fuse ROM)

Figure 8-53 RTRIM_B Register

7	6	5	4	3	2	1	0
RTRIM_B
R/W-0x0

Table 8-91 RTRIM_B Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	RTRIM_B	R/W	0x0	This register controls the INB± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

8.5.7.35 RTRIM_C Register (Address = 0x80) [reset = 0x0]

RTRIM_C is shown in Figure 8-54 and described in Table 8-92.

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Resistor Trim for INC (default from Fuse ROM)

Figure 8-54 RTRIM_C Register

7	6	5	4	3	2	1	0
RTRIM_C
R/W-0x0

Table 8-92 RTRIM_C Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	RTRIM_C	R/W	0x0	This register controls the INC± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

8.5.7.36 RTRIM_D Register (Address = 0x81) [reset = 0x0]

RTRIM_D is shown in Figure 8-55 and described in Table 8-93.

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Resistor Trim for IND (default from Fuse ROM)

Figure 8-55 RTRIM_D Register

7	6	5	4	3	2	1	0
RTRIM_D
R/W-0x0

Table 8-93 RTRIM_D Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	RTRIM_D	R/W	0x0	This register controls the IND± ADC input termination trim. After reset, the factory trimmed value can be read and adjusted as required.

8.5.7.37 ADC Source Control Delay (Address = 0x9A) [reset = 0x08]

ADC_SRC_DLY is shown in AC_SRC_DLY Register and described in ADC_SRC_DLY Register Field Descriptions. Only change this register while CAL_EN is 0.

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ADC Dither Control (default from Fuse ROM)

Figure 8-56 ADC_SRC_DLY Register

7	6	5	4	3	2	1	0
RESERVED
R/W-0x0			R/W-0x08

Table 8-94 ADC_SRC_DLY Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

RESERVED

R/W

0x0

Must write default value.

4:0

ADC_SRC_DLY

R/W

0x08

Adjusts how long two ADCs will sample the same input at the same clock phase during background ADC swaps.

The default value is appropriate for all ADCCLK frequencies. If using a reduced ADCCLK frequency, ADC_SRC_DLY can be set to 7 to reduce the glitch duration during fast background ADC swaps, however there is a greater risk of having a large glitch amplitude.

Two ADCs will sample the same input for 4+2*ADC_SRC_DLY ADCCLK cycles.

ADC_SRC_DLY can be programmed from 0 to 31.

8.5.7.38 MUX Select Delay Register (Address = 0x9B) [reset = 0x07]

MUX_SEL_DLY is shown in MUX_SEL_DLY Register and described in MUX_SEL_DLY Register Field Descriptions.

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Figure 8-57 MUX_SEL_DLY Register

7	6	5	4	3	2	1	0
RESERVED			MUX_SEL_DLY
R/W-0x0			R/W-0x07

Table 8-95 MUX_SEL_DLY Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	MUX_SEL_DLY	R/W	0x07	Adjusts the delay added to the internal mux selection signal. This signal controls multiplexors that steer ADC core output data into the encoders. This delay only applies during background ADC swaps. This delay needs to be tuned to swap between sample streams during a small window of time when both sample streams are valid. MUX_SEL_DLY can be programmed from 0 to 31.

8.5.7.39 ADC_DITH Register (Address = 0x9D) [reset = 0x0]

ADC_DITH is shown in Figure 8-58 and described in Table 8-96.

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ADC Dither Control (default from Fuse ROM)

Figure 8-58 ADC_DITH Register

7	6	5	4	3	2	1	0
RESERVED					ADC_DITH_ERR	ADC_DITH_AMP	ADC_DITH_EN
R/W-0x0					R/W-0x0	R/W-0x0	R/W-0x0

Table 8-96 ADC_DITH Register Field Descriptions

Bit	Field	Type	Reset	Description
7:3	RESERVED	R/W	0x0	Must write default value.
2	ADC_DITH_ERR	R/W	0x0	Small rounding errors may occur when subtracting the dither signal. The error can be chosen to either slightly degrade SNR or to slightly increase the DC offset and FS/2 spur. In addition, the FS/4 spur will also be increased slightly while in single channel mode. 0 : Rounding error degrades SNR 1 : Rounding error degrades DC offset, FS/2 spur and FS/4 spur
1	ADC_DITH_AMP	R/W	0x0	0 : Small dither for better SNR (default) 1 : Large dither for better spurious performance
0	ADC_DITH_EN	R/W	0x0	Set this bit to enable ADC dither. Dither can improve spurious performance at the expense of slightly degraded SNR. The dither amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR and spurious performance.

8.5.7.40 LSB_CTRL Register (Address = 0x160) [reset = 0x00]

LSB_CTRL is shown in Figure 8-59 and described in Table 8-97.

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LSB Control Bit Output (default: 0x00)

Figure 8-59 LSB_CTRL Register

7	6	5	4	3	2	1	0
RESERVED							TIME_STAMP_EN
R/W-0x0							R/W-0x0

Table 8-97 LSB_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R/W	0x0	Must write default value.
0	TIME_STAMP_EN	R/W	0x0	When set, the transport layer transmits the timestamp signal on the LSB of the output samples. The latency of the timestamp signal (through the entire chip) should match the latency of the analog ADC inputs. Please also set TMSTP_RECV_EN when using TIME_STAMP_EN. Note 1: The control bit is placed on the LSB of the JESD204C samples. In some cases, the JESD204C sample width (N) is greater than the sample width from the ADC. In these cases, the control bit does not replace the LSB of the ADC sample since it is placed at the LSB of the N-bit field). Note 2: The control bit that is enabled by this register is never advertised in the ILA (CS is 0 in the ILA).

8.5.7.41 JESD_EN Register (Address = 0x200) [reset = 0x01]

JESD_EN is shown in Figure 8-60 and described in Table 8-98.

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JESD204C Subsystem Enable (default: 0x01)

Figure 8-60 JESD_EN Register

7	6	5	4	3	2	1	0
RESERVED							JESD_EN
R/W-0x0							R/W-0x1

Table 8-98 JESD_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R/W	0x0	Must write default value.
0	JESD_EN	R/W	0x1	0 : Disable JESD204C interface 1 : Enable JESD204C interface Note: Before altering other JESD204C registers, you must clear JESD_EN. When JESD_EN is 0, the block is held in reset and the serializers are powered down. The clocks are gated off to save power. The LMFC/LEMC counter is also held in reset, so SYSREF will not align the LMFC/LEMC. Note: Always set CAL_EN before setting JESD_EN. Note: Always clear JESD_EN before clearing CAL_EN.

8.5.7.42 JMODE Register (Address = 0x201) [reset = 0x00]

JMODE is shown in Figure 8-61 and described in Table 8-99.

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JESD204C Mode (default: 0x00)

Figure 8-61 JMODE Register

7	6	5	4	3	2	1	0
RESERVED		JMODE
R/W-0x0		R/W-0x0

Table 8-99 JMODE Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R/W	0x0	Must write default value.
5:0	JMODE	R/W	0x0	Specifies the JESD204C output mode. See JESD204C Mode table. Note: This register should only be changed when JESD_EN=0 and CAL_EN=0.

8.5.7.43 KM1 Register (Address = 0x202) [reset = 0x1F]

KM1 is shown in Figure 8-62 and described in Table 8-100.

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JESD204C K Parameter (minus 1) (default: 0x1F)

Figure 8-62 KM1 Register

7	6	5	4	3	2	1	0
KM1
R/W-0x1F

Table 8-100 KM1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	KM1	R/W	0x1F	K is the number of frames per multiframe and this register must be programmed as K-1. Depending on the JMODE setting, there are constraints on the legal values of K (see K parameter in JESD204C Mode table). The default value is KM1=31, which corresponds to K=32. Note: For modes using the 64B/66B link layer, the KM1 register is ignored and the value of K is determined from E and F (which are derived from JMODE). The effective value of K is 256*E/F. Note: This register should only be changed when JESD_EN is 0.

8.5.7.44 JSYNC_N Register (Address = 0x203) [reset = 0x01]

JSYNC_N is shown in Figure 8-63 and described in Table 8-101.

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JESD204C Manual Sync Request (default: 0x01)

Figure 8-63 JSYNC_N Register

7	6	5	4	3	2	1	0
RESERVED							JSYNC_N
R/W-0x0							R/W-0x1

Table 8-101 JSYNC_N Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R/W	0x0	Must write default value.
0	JSYNC_N	R/W	0x1	Set this bit to 0 to request JESD204C synchronization (equivalent to the SYNC~ signal being asserted). For normal operation, leave this bit set to 1. Note: The JSYNC_N register can always generate a synchronization request, regardless of the SYNC_SEL register. However, if the selected sync pin is stuck low, you cannot de-assert the synchronization request unless you program SYNC_SEL=2.

8.5.7.45 JCTRL Register (Address = 0x204) [reset = 0x03]

JCTRL is shown in Figure 8-64 and described in Table 8-102.

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JESD204C Control (default: 0x03)

Figure 8-64 JCTRL Register

7	6	5	4	3	2	1	0
RESERVED			ALT_LANES	SYNC_SEL		SFORMAT	SCR
R/W-0x0			R/W-0x0	R/W-0x0		R/W-0x1	R/W-0x1

Table 8-102 JCTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4	ALT_LANES	R/W	0x0	0 : Normal lane mapping (default) as shown in the JESD204C output mode section. Lanes 0 thru L-1 are used. 1 : Alternate lane mapping (use upper lanes). Lanes 4 to 4+L-1 are used. Lanes 0 to 3 are unused. This option is only supported when JMODE selects a mode that uses 4 or less lanes per link (L<=4). The behavior is undefined for modes that use more than 4 lanes.
3:2	SYNC_SEL	R/W	0x0	0 : Use the SYNCSE input for SYNC~ function (default) 1 : Use the TMSTP± input for SYNC~ function. TMSTP_RECV_EN must also be set. 2 : Do not use any SYNC~ input pin (use JSYNC_N as a software SYNC~)
1	SFORMAT	R/W	0x1	Output sample format for JESD204C samples 0 : Offset binary 1 : Signed 2’s complement (default)
0	SCR	R/W	0x1	0 : 8B/10B Scrambler disabled (applies only to 8B/10B modes) 1 : 8B/10B Scrambler enabled (default) Note 1: The 8b/10b scrambler is recommended to improve spurious noise and specify certain sample payloads cannot prevent the JESD204C receiver from detecting incorrect code-group or lane alignment. 64B/66B modes always use scrambling. This register does not apply to 64B/66B modes. Note: This register should only be changed when JESD_EN is 0.

8.5.7.46 JTEST Register (Address = 0x205) [reset = 0x00]

JTEST is shown in Figure 8-65 and described in Table 8-103.

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JESD204C Test Control (default: 0x00)

Figure 8-65 JTEST Register

7	6	5	4	3	2	1	0
RESERVED			JTEST
R/W-0x0			R/W-0x0

Table 8-103 JTEST Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	JTEST	R/W	0x0	0 : Test mode disabled. Normal operation (default) 1 : PRBS7 test mode 2 : PRBS15 test mode 3 : PRBS23 test mode 4 : Ramp test mode 5 : Transport Layer test mode 6 : D21.5 test mode 7 : K28.5 test mode* 8 : Repeated ILA test mode* 9 : Modified RPAT test mode* 10: Serial outputs held low 11: Serial outputs held high 12: RESERVED 13: PRBS9 test mode 14: PRBS31 test mode 15: Clock test pattern (0x00FF) 16: K28.7 test mode* 17-31: RESERVED * These test modes are only supported when JMODE is selecting a mode that utilizes 8B/10B encoding. Note: This register should only be changed when JESD_EN is 0.

8.5.7.47 DID Register (Address = 0x206) [reset = 0x00]

DID is shown in Figure 8-66 and described in Table 8-104.

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JESD204C DID Parameter (default: 0x00)

Figure 8-66 DID Register

7	6	5	4	3	2	1	0
DID
R/W-0x0

Table 8-104 DID Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DID	R/W	0x0	Specifies the DID (Device ID) value that is transmitted during the second multiframe of the JESD204B ILA. Note: This register should only be changed when JESD_EN is 0.

8.5.7.48 FCHAR Register (Address = 0x207) [reset = 0x00]

FCHAR is shown in Figure 8-67 and described in Table 8-105.

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JESD204C Frame Character (default: 0x00)

Figure 8-67 FCHAR Register

7	6	5	4	3	2	1	0
RESERVED						FCHAR
R/W-0x0						R/W-0x0

Table 8-105 FCHAR Register Field Descriptions

Bit	Field	Type	Reset	Description
7:2	RESERVED	R/W	0x0	Must write default value.
1:0	FCHAR	R/W	0x0	Specify which comma character is used to denote end-of-frame. This character is transmitted opportunistically. This only applies to modes that utilize 8B/10B encoding. 0 : Use K28.7 (default) (JESD204C compliant) 1 : Use K28.1 (not JESD204C compliant) 2 : Use K28.5 (not JESD204C compliant) 3 : Reserved When using a JESD204C receiver, always use FCHAR=0. When using a general purpose 8B/10B receiver, the K28.7 character may cause issues. When K28.7 is combined with certain data characters, a false, misaligned comma character can result, and some receivers will re-align to the false comma. To avoid this, program FCHAR to 1 or 2. Note: This register should only be changed when JESD_EN is 0.

8.5.7.49 JESD_STATUS Register (Address = 0x208) [reset = 0x0]

JESD_STATUS is shown in Figure 8-68 and described in Table 8-106.

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JESD204C / System Status Register

Figure 8-68 JESD_STATUS Register

7	6	5	4	3	2	1	0
RESERVED	LINK_UP	SYNC_STATUS	REALIGNED	ALIGNED	SPLL_LOCKED	RESERVED	CPLL_LOCKED
R/W-0x0	R/W-0x0	R/W-0x0	R/W-0x0	R/W-0x0	R/W-0x0	R/W-0x0	R/W-0x0

Table 8-106 JESD_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R/W	0x0
6	LINK_UP	R/W	0x0	When set, indicates that the JESD204C link is up.
5	SYNC_STATUS	R/W	0x0	Returns the state of the JESD204C SYNC~ signal. 0 : SYNC~ asserted 1 : SYNC~ de-asserted
4	REALIGNED	R/W	0x0	When high, indicates that the digital block clock, frame clock, or multiframe clock phase was realigned by SYSREF. Writing a 1 to this bit will clear it.
3	ALIGNED	R/W	0x0	When high, indicates that the multiframe (LMFC) clock phase has been established by SYSREF. The first SYSREF event after enabling the JESD204B encoder will set this bit. Writing a 1 to this bit will clear it.
2	SPLL_LOCKED	R/W	0x0	When high, indicates that the SerDes PLL (S-PLL) is locked.
1	RESERVED	R/W	0x0
0	CPLL_LOCKED	R/W	0x0	When high, indicates that the converter PLL (C-PLL) is locked.

8.5.7.50 CH_EN Register (Address = 0x209) [reset = 0x03]

CH_EN is shown in Figure 8-69 and described in Table 8-107.

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JESD204C Channel Enable (default: 0x03)

Figure 8-69 CH_EN Register

7	6	5	4	3	2	1	0
RESERVED					SINGLE_CH_EN	CD_EN	AB_EN
R/W-0x0					R/W-0x0	R/W-0x1	R/W-0x1

Table 8-107 CH_EN Register Field Descriptions

Bit	Field	Type	Reset	Description
7:3	RESERVED	R/W	0x0	Must write default value.
2	SINGLE_CH_EN	R/W	0x0	When set, single channel mode is enabled and channels B, C and D are disabled. AB_EN must be set to 1.
1	CD_EN	R/W	0x1	When set, the C and D channels are enabled. Set to 0 to disable channels C and D. Set this bit to enable dual channel operation.
0	AB_EN	R/W	0x1	When set, the A and B channels are enabled. Set to 0 to disable channel A and B. Important notes: 1. You must set CAL_EN=0 and JESD_EN=0 before changing CH_EN. 2. Do not use this register to disable (power down) all channels since this state is undefined. Instead use the MODE register to power down the full device. 3. When either pair of channels is disabled, the JESD204C link will scale down the number of lanes and converters: L = ceiling(Lx/2) and M = Mx/2. If Lx is odd, tail bits are added to the end of the highest lane to pad out the frame (as per the JESD204C standard). 4. When AB_EN=0, the samples for channels C & D are placed within the JESD204C frame where the A & B samples would normally be located.

8.5.7.51 SHMODE Register (Address = 0x20F) [reset = 0x00]

SHMODE is shown in Figure 8-70 and described in Table 8-108.

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JESD204C Sync Word Mode (default: 0x00)

Figure 8-70 SHMODE Register

7	6	5	4	3	2	1	0
RESERVED						SHMODE
R/W-0x0						R/W-0x0

Table 8-108 SHMODE Register Field Descriptions

Bit	Field	Type	Reset	Description
7:2	RESERVED	R/W	0x0	Must write default value.
1:0	SHMODE	R/W	0x0	Select the mode for the 64B/66B sync word (32 bits of data per multi-block). This only applies when JMODE is selecting a 64B/66B mode. 0 : Transmit CRC-12 signal (default setting) 1 : RESERVED 2 : Transmit FEC signal 3 : RESERVED Note: This device does not support any JESD204C command features. All command fields will be set to zero (idle headers). Note: This register should only be changed when JESD_EN is 0.

8.5.7.52 SYNC_THRESH Register (Address = 0x210) [reset = 0x03]

SYNC_THRESH is shown in Figure 8-71 and described in Table 8-109.

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JESD204C SYNC~ Threshold (default: 0x03)

Figure 8-71 SYNC_THRESH Register

7	6	5	4	3	2	1	0
RESERVED			SYNC_THRESH
R/W-0x0			R/W-0x3

Table 8-109 SYNC_THRESH Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	SYNC_THRESH	R/W	0x3	This register defines how many times the SYNC~ signal must be sampled low before the JESD204C transmitter interprets it as a synchronization request. The SYNC~ signal is sampled by the link clock (fS/2). If SYNC~ is sampled low for SYNC_THRESH+1 consecutive clock cycles, it will be interpreted as a synchronization request. Refer to JESD204C section 8.8.2 for more details. If SYNC~ is sampled low for less than SYNC_THRESH+1 clock cycles, it is considered to be an error report and is ignored. Note: This register should only be changed when JESD_EN is 0. Note: Since this design does not do anything with an error reported on the SYNC~ interface, it is recommended that error reporting be disabled on the receiver and SYNC_THRESH programmed to 0. This provides the fastest response time for synchronization requests.

8.5.7.53 OVR_TH Register (Address = 0x211) [reset = 0xF2]

OVR_TH is shown in Figure 8-72 and described in Table 8-110.

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Over-range Threshold (default: 0xF2)

Figure 8-72 OVR_TH Register

7	6	5	4	3	2	1	0
OVR_TH
R/W-0xF2

Table 8-110 OVR_TH Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	OVR_TH	R/W	0xF2	This parameter defines the absolute sample level that causes the over-range outputs to be asserted. The detection level in dBFS (peak) is 20log10(OVR_TH/256) (Default: 0xF2 = 242-> -0.5dBFS)

8.5.7.54 OVR_CFG Register (Address = 0x213) [reset = 0x07]

OVR_CFG is shown in Figure 8-73 and described in Table 8-111.

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Over-range Enable / Hold Off (default: 0x07)

Figure 8-73 OVR_CFG Register

7	6	5	4	3	2	1	0
RESERVED				OVR_EN	OVR_N
R/W-0x0				R/W-0x0	R/W-0x7

Table 8-111 OVR_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R/W	0x0	Must write default value.
3	OVR_EN	R/W	0x0	Enables over-range status output pins when set high. The ORA, ORB, ORC and ORD outputs are held low when OVR_EN is set low.
2:0	OVR_N	R/W	0x7	Program this register to adjust the pulse extension for the ORA, ORB, ORC and ORD outputs. The minimum pulse duration of the over-range outputs is 4 * 2^OVR_N sampling cycles. Incrementing this field doubles the monitoring period.

8.5.7.55 INIT_STATUS Register (Address = 0x270) [reset = 0x0]

INIT_STATUS is shown in Figure 8-74 and described in Table 8-112.

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Initialization Status (read-only)

Figure 8-74 INIT_STATUS Register

7	6	5	4	3	2	1	0
RESERVED							INIT_DONE
R-0x0							R-0x0

Table 8-112 INIT_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R	0x0
0	INIT_DONE	R	0x0	Returns 1 when the initialization logic has finished initializing the device. This indicates that it is now safe to proceed with startup. No SPI transactions should be performed before INIT_DONE returns 1 (except SOFT_RESET).

8.5.7.56 LOW_POWER2 Register (Address = 0x29A) [reset = 0x0F]

LOW_POWER2 is shown in Figure 8-75 and described in Table 8-113.

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Low Power Mode 2 (default: 0x0F)

Figure 8-75 LOW_POWER2 Register

7	6	5	4	3	2	1	0
LOW_POW_MODE2
R/W-0xF

Table 8-113 LOW_POWER2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	LOW_POW_MODE2	R/W	0xF	Set this register along with LOW_POWER1, LOW_POWER3 and LOW_POWER4 to enable Low Power Mode. All registers must be set together. Calibration must be performed after changing the operating mode: 0x06 : Low Power Mode 0x0F : High Performance Mode (default) All other values are RESERVED Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this register.

8.5.7.57 LOW_POWER3 Register (Address = 0x29B) [reset = 0x04]

LOW_POWER3 is shown in Figure 8-76 and described in Table 8-114.

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Low Power Mode 3 (default: 0x04)

Figure 8-76 LOW_POWER3 Register

7	6	5	4	3	2	1	0
LOW_POW_MODE3
R/W-0x4

Table 8-114 LOW_POWER3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	LOW_POW_MODE3	R/W	0x4	Set this register along with LOW_POWER1, LOW_POWER2 and LOW_POWER4 to enable Low Power Mode. All registers must be set together. Calibration must be performed after changing the operating mode: 0x00 : Low Power Mode 0x04 : High Performance Mode (default) All other values are RESERVED Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this register.

8.5.7.58 LOW_POWER4 Register (Address = 0x29C) [reset = 0x1B]

LOW_POWER4 is shown in Figure 8-77 and described in Table 8-115.

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Low Power Mode 4 (default: 0x1B)

Figure 8-77 LOW_POWER4 Register

7	6	5	4	3	2	1	0
LOW_POW_MODE4
R/W-0x1B

Table 8-115 LOW_POWER4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	LOW_POW_MODE4	R/W	0x1B	Set this register along with LOW_POWER1, LOW_POWER2 and LOW_POWER3 to enable Low Power Mode. All registers must be set together. Calibration must be performed after changing the operating mode: 0x14 : Low Power Mode 0x1B : High Performance Mode (default) All other values are RESERVED Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this register.

8.5.7.59 ALARM Register (Address = 0x2C0) [reset = 0x0]

ALARM is shown in Figure 8-78 and described in Table 8-116.

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Alarm Interrupt (read-only)

Figure 8-78 ALARM Register

7	6	5	4	3	2	1	0
RESERVED							ALARM
R-0x0							R-0x0

Table 8-116 ALARM Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R	0x0
0	ALARM	R	0x0	This bit returns a ‘1’ whenever any alarm occurs that is unmasked in the ALM_STATUS register. Use ALM_MASK to mask (disable) individual alarms. CAL_STATUS_SEL can be used to drive the ALARM bit onto the CALSTAT output pin to provide a hardware alarm interrupt signal.

8.5.7.60 ALM_STATUS Register (Address = 0x2C1) [reset = 0x3F]

ALM_STATUS is shown in Figure 8-79 and described in Table 8-117.

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Alarm Status (default: 0x3F, write to clear)

Figure 8-79 ALM_STATUS Register

7	6	5	4	3	2	1	0
RESERVED		FIFO_ALM	SPLL_ALM	LINK_ALM	REALIGNED_ALM	RESERVED	CLK_ALM
R/W-0x0		R/W-0x1	R/W-0x1	R/W-0x1	R/W-0x1	R/W-0x1	R/W-0x1

Table 8-117 ALM_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R/W	0x0
5	FIFO_ALM	R/W	0x1	FIFO overflow/underflow alarm: This bit is set whenever an active JESD204C lane FIFO experiences an underflow or overflow condition. Write a ‘1’ to clear this bit. To inspect which lane generated the alarm, read FIFO_LANE_ALM.
4	SPLL_ALM	R/W	0x1	S-PLL Lock Lost Alarm: This bit is set whenever the SerDes S-PLL is not locked. Write a ‘1’ to clear this bit.
3	LINK_ALM	R/W	0x1	Link Alarm: This bit is set whenever the JESD204C link is enabled, but is not in the DATA_ENC state (8B/10B modes). In 64B/66B modes, there is no DATA_ENC state, so this alarm will fire when the link first starts up, and will also fire if any event causes a FIFO/Serializer realignment. Write a ‘1’ to clear this bit.
2	REALIGNED_ALM	R/W	0x1	Realigned Alarm: This bit is set whenever SYSREF causes the internal clocks (including the LMFC/LEMC) to be realigned. Write a ‘1’ to clear this bit.
1	RESERVED	R/W	0x1
0	CLK_ALM	R/W	0x1	Clock Alarm: This bit can be used to detect an upset to the internal digital block and JESD204C clocks. This bit is set whenever the internal clock dividers for the A and B channels do not match the C and D channels. Write a ‘1’ to clear this bit. Refer to the alarm section for the proper usage of this register. Note: After power-on reset or soft-reset, all alarm bits are set to ‘1.’ Note: When JESD_EN=0, all alarms (except CLK_ALM) are undefined. It is recommended that the user clears the alarms after setting JESD_EN=1.

8.5.7.61 ALM_MASK Register (Address = 0x2C2) [reset = 0x3F]

ALM_MASK is shown in Figure 8-80 and described in Table 8-118.

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Alarm Mask Register (default: 0x3F)

Figure 8-80 ALM_MASK Register

7	6	5	4	3	2	1	0
RESERVED		MASK_FIFO_ALM	MASK_PLL_ALM	MASK_LINK_ALM	MASK_REALIGNED_ALM	RESERVED	MASK_CLK_ALM
R/W-0x0		R/W-0x1	R/W-0x1	R/W-0x1	R/W-0x1	R/W-0x1	R/W-0x1

Table 8-118 ALM_MASK Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R/W	0x0	Must write default value.
5	MASK_FIFO_ALM	R/W	0x1	When set, FIFO_ALM is masked and will not impact the ALARM register bit.
4	MASK_PLL_ALM	R/W	0x1	When set, PLL_ALM is masked and will not impact the ALARM register bit.
3	MASK_LINK_ALM	R/W	0x1	When set, LINK_ALM is masked and will not impact the ALARM register bit.
2	MASK_REALIGNED_ALM	R/W	0x1	When set, REALIGNED_ALM is masked and will not impact the ALARM register bit.
1	RESERVED	R/W	0x1	Must write default value.
0	MASK_CLK_ALM	R/W	0x1	When set, CLK_ALM is masked and will not impact the ALARM register bit.

8.5.7.62 FIFO_LANE_ALM Register (Address = 0x2C4) [reset = 0xFF]

FIFO_LANE_ALM is shown in Figure 8-81 and described in Table 8-119.

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FIFO Overflow/Underflow Alarm (default: 0xFF)

Figure 8-81 FIFO_LANE_ALM Register

7	6	5	4	3	2	1	0
FIFO_LANE_ALM
R/W-0xFF

Table 8-119 FIFO_LANE_ALM Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	FIFO_LANE_ALM	R/W	0xFF	FIFO_LANE_ALM[i] is set if the FIFO for lane i experiences overflow or underflow. Use this register to determine which lane(s) generated an alarm. Writing a ‘1’ to any bit in this register will clear the alarm (the alarm may immediately trip again if the overflow/underflow condition persists). Writing a ‘1’ to the FIFO_ALM register will clear all bits of this register.

8.5.7.63 OFS0 Register (Address = 0x330) [reset = 0x0]

OFS0 is shown in Figure 8-82 and described in Table 8-120.

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Offset Adjustment for ADC0 (default from Fuse ROM)

Figure 8-82 OFS0 Register

15	14	13	12	11	10	9	8
RESERVED				OFS0
R/W-0x0				R/W-0x0

7	6	5	4	3	2	1	0
OFS0
R/W-0x0

Table 8-120 OFS0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R/W	0x0	Must write default value.
11:0	OFS0	R/W	0x0	Offset adjustment value applied to ADC0. The format is unsigned. Important note: Do not access any OFS* registers if the calibration system is performing offset calibration. Case 1: If CAL_BGOS or CAL_BG is 0 and CAL_OS is 1, you may access OFS* registers after FG_DONE goes high. Case 2: If CAL_BG=1 and CAL_BGOS=1, you should not access the OFS* registers. For background calibration without continuous offset calibration, set CAL_OS to 1 and CAL_BG to 1, but keep CAL_BGOS set to 0. This will still calibrate the offset of the spare ADC cores during the foreground offset calibration step. Case 3: If none of the above conditions apply, you may access the OFS* registers without waiting.

8.5.7.64 OFS1 Register (Address = 0x332) [reset = 0x0]

OFS1 is shown in Figure 8-83 and described in Table 8-121.

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Offset Adjustment for ADC1 (default from Fuse ROM)

Figure 8-83 OFS1 Register

15	14	13	12	11	10	9	8
RESERVED				OFS1
R/W-0x0				R/W-0x0

7	6	5	4	3	2	1	0
OFS1
R/W-0x0

Table 8-121 OFS1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R/W	0x0	Must write default value.
11:0	OFS1	R/W	0x0	Offset adjustment value applied to ADC1.

8.5.7.65 OFS2A Register (Address = 0x334) [reset = 0x0]

OFS2A is shown in Figure 8-84 and described in Table 8-122.

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Offset Adjustment for ADC2 (INA±) (default from Fuse ROM)

Figure 8-84 OFS2A Register

15	14	13	12	11	10	9	8
RESERVED				OFS2A
R/W-0x0				R/W-0x0

7	6	5	4	3	2	1	0
OFS2A
R/W-0x0

Table 8-122 OFS2A Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R/W	0x0	Must write default value.
11:0	OFS2A	R/W	0x0	Offset adjustment value applied to ADC2 when sampling INA±.

8.5.7.66 OFS2B Register (Address = 0x336) [reset = 0x0]

OFS2B is shown in Figure 8-85 and described in Table 8-123.

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Offset Adjustment for ADC2 (INB±) (default from Fuse ROM)

Figure 8-85 OFS2B Register

15	14	13	12	11	10	9	8
RESERVED				OFS2B
R/W-0x0				R/W-0x0

7	6	5	4	3	2	1	0
OFS2B
R/W-0x0

Table 8-123 OFS2B Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R/W	0x0	Must write default value.
11:0	OFS2B	R/W	0x0	Offset adjustment value applied to ADC2 when sampling INB±.

8.5.7.67 OFS3C Register (Address = 0x338) [reset = 0x0]

OFS3C is shown in Figure 8-86 and described in Table 8-124.

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Offset Adjustment for ADC3 (INC±) (default from Fuse ROM)

Figure 8-86 OFS3C Register

15	14	13	12	11	10	9	8
RESERVED				OFS3C
R/W-0x0				R/W-0x0

7	6	5	4	3	2	1	0
OFS3C
R/W-0x0

Table 8-124 OFS3C Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R/W	0x0	Must write default value.
11:0	OFS3C	R/W	0x0	Offset adjustment value applied to ADC3 when sampling INC±.

8.5.7.68 OFS3D Register (Address = 0x33A) [reset = 0x0]

OFS3D is shown in Figure 8-87 and described in Table 8-125.

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Offset Adjustment for ADC3 (IND±) (default from Fuse ROM)

Figure 8-87 OFS3D Register

15	14	13	12	11	10	9	8
RESERVED				OFS3D
R/W-0x0				R/W-0x0

7	6	5	4	3	2	1	0
OFS3D
R/W-0x0

Table 8-125 OFS3D Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R/W	0x0	Must write default value.
11:0	OFS3D	R/W	0x0	Offset adjustment value applied to ADC3 when sampling IND±.

8.5.7.69 OFS4 Register (Address = 0x33C) [reset = 0x0]

OFS4 is shown in Figure 8-88 and described in Table 8-126.

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Offset Adjustment for ADC4 (default from Fuse ROM)

Figure 8-88 OFS4 Register

15	14	13	12	11	10	9	8
RESERVED				OFS4
R/W-0x0				R/W-0x0

7	6	5	4	3	2	1	0
OFS4
R/W-0x0

Table 8-126 OFS4 Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R/W	0x0	Must write default value.
11:0	OFS4	R/W	0x0	Offset adjustment value applied to ADC4.

8.5.7.70 OFS5 Register (Address = 0x33E) [reset = 0x0]

OFS5 is shown in Figure 8-89 and described in Table 8-127.

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Offset Adjustment for ADC5 (default from Fuse ROM)

Figure 8-89 OFS5 Register

15	14	13	12	11	10	9	8
RESERVED				OFS5
R/W-0x0				R/W-0x0

7	6	5	4	3	2	1	0
OFS5
R/W-0x0

Table 8-127 OFS5 Register Field Descriptions

Bit	Field	Type	Reset	Description
15:12	RESERVED	R/W	0x0	Must write default value.
11:0	OFS5	R/W	0x0	Offset adjustment value applied to ADC5.

8.5.7.71 GAIN0 Register (Address = 0x360) [reset = 0x0]

GAIN0 is shown in Figure 8-90 and described in Table 8-128.

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Fine Gain Adjust for ADC0 (default from Fuse ROM)

Figure 8-90 GAIN0 Register

7	6	5	4	3	2	1	0
RESERVED			GAIN0
R/W-0x0			R/W-0x0

Table 8-128 GAIN0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	GAIN0	R/W	0x0	Fine gain adjustment for ADC0.

8.5.7.72 GAIN1 Register (Address = 0x361) [reset = 0x0]

GAIN1 is shown in Figure 8-91 and described in Table 8-129.

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Fine Gain Adjust for ADC1 (default from Fuse ROM)

Figure 8-91 GAIN1 Register

7	6	5	4	3	2	1	0
RESERVED			GAIN1
R/W-0x0			R/W-0x0

Table 8-129 GAIN1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	GAIN1	R/W	0x0	Fine gain adjustment for ADC1.

8.5.7.73 GAIN2A Register (Address = 0x362) [reset = 0x0]

GAIN2A is shown in Figure 8-92 and described in Table 8-130.

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Fine Gain Adjust for ADC2 (INA±) (default from Fuse ROM)

Figure 8-92 GAIN2A Register

7	6	5	4	3	2	1	0
RESERVED			GAIN2A
R/W-0x0			R/W-0x0

Table 8-130 GAIN2A Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	GAIN2A	R/W	0x0	Fine gain adjustment for ADC2 when sampling INA±.

8.5.7.74 GAIN2B Register (Address = 0x363) [reset = 0x0]

GAIN2B is shown in Figure 8-93 and described in Table 8-131.

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Fine Gain Adjust for ADC2 (INB±) (default from Fuse ROM)

Figure 8-93 GAIN2B Register

7	6	5	4	3	2	1	0
RESERVED			GAIN2B
R/W-0x0			R/W-0x0

Table 8-131 GAIN2B Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	GAIN2B	R/W	0x0	Fine gain adjustment for ADC2 when sampling INB±.

8.5.7.75 GAIN3C Register (Address = 0x364) [reset = 0x0]

GAIN3C is shown in Figure 8-94 and described in Table 8-132.

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Fine Gain Adjust for ADC3 (INC±) (default from Fuse ROM)

Figure 8-94 GAIN3C Register

7	6	5	4	3	2	1	0
RESERVED			GAIN3C
R/W-0x0			R/W-0x0

Table 8-132 GAIN3C Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	GAIN3C	R/W	0x0	Fine gain adjustment for ADC3 when sampling INC±.

8.5.7.76 GAIN3D Register (Address = 0x365) [reset = 0x0]

GAIN3D is shown in Figure 8-95 and described in Table 8-133.

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Fine Gain Adjust for ADC3 (IND±) (default from Fuse ROM)

Figure 8-95 GAIN3D Register

7	6	5	4	3	2	1	0
RESERVED			GAIN3D
R/W-0x0			R/W-0x0

Table 8-133 GAIN3D Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	GAIN3D	R/W	0x0	Fine gain adjustment for ADC3 when sampling IND±.

8.5.7.77 GAIN4 Register (Address = 0x366) [reset = 0x0]

GAIN4 is shown in Figure 8-96 and described in Table 8-134.

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Fine Gain Adjust for ADC4 (default from Fuse ROM)

Figure 8-96 GAIN4 Register

7	6	5	4	3	2	1	0
RESERVED			GAIN4
R/W-0x0			R/W-0x0

Table 8-134 GAIN4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	GAIN4	R/W	0x0	Fine gain adjustment for ADC4.

8.5.7.78 GAIN5 Register (Address = 0x367) [reset = 0x0]

GAIN5 is shown in Figure 8-97 and described in Table 8-135.

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Fine Gain Adjust for ADC5 (default from Fuse ROM)

Figure 8-97 GAIN5 Register

7	6	5	4	3	2	1	0
RESERVED			GAIN5
R/W-0x0			R/W-0x0

Table 8-135 GAIN5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R/W	0x0	Must write default value.
4:0	GAIN5	R/W	0x0	Fine gain adjustment for ADC5.