SBAS997A February   2020  – June 2021 ADC09DJ1300-Q1 , ADC09QJ1300-Q1 , ADC09SJ1300-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Comparison
      2. 8.3.2 Analog Input
        1. Analog Input Protection
        2. Full-Scale Voltage (VFS) Adjustment
        3. Analog Input Offset Adjust
        4. ADC Core
          1. ADC Core Calibration
          2. ADC Theory of Operation
          3. Analog Reference Voltage
          4. ADC Over-range Detection
          5. Code Error Rate (CER)
        5. Temperature Monitoring Diode
        6. Timestamp
        7. Clocking
          1. Converter PLL (C-PLL) for Sampling Clock Generation
          2. LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
          3. Optional CMOS Clock Outputs (ORC, ORD)
          4. SYSREF for JESD204C Subclass-1 Deterministic Latency
            1. SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
            2. SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        8. JESD204C Interface
          1.  Transport Layer
          2.  Scrambler
          3.  Link Layer
          4.  8B/10B Link Layer
            1. Data Encoding (8B/10B)
            2. Multiframes and the Local Multiframe Clock (LMFC)
            3. Code Group Synchronization (CGS)
            4. Initial Lane Alignment Sequence (ILAS)
            5. Frame and Multiframe Monitoring
          5.  64B/66B Link Layer
            1. 64B/66B Encoding
            2. Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. Cyclic Redundancy Check (CRC) Mode
                2. Forward Error Correction (FEC) Mode
            3. Initial Lane Alignment
            4. Block, Multiblock and Extended Multiblock Alignment Monitoring
          6.  Physical Layer
            1. SerDes Pre-Emphasis
          7.  JESD204C Enable
          8.  Multi-Device Synchronization and Deterministic Latency
          9.  Operation in Subclass 0 Systems
          10. Alarm Monitoring
            1. Clock Upset Detection
            2. FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Mode and High Performance Mode
      2. 8.4.2 JESD204C Modes
        1. JESD204C Transport Layer Data Formats
        2. 64B/66B Sync Header Stream Configuration
        3. Redundant Data Mode (Alternate Lanes)
      3. 8.4.3 Power-Down Modes
      4. 8.4.4 Test Modes
        1.  Serializer Test-Mode Details
        2.  PRBS Test Modes
        3.  Clock Pattern Mode
        4.  Ramp Test Mode
        5.  Short and Long Transport Test Mode
          1. Short Transport Test Pattern
        6.  D21.5 Test Mode
        7.  K28.5 Test Mode
        8.  Repeated ILA Test Mode
        9.  Modified RPAT Test Mode
        10. Calibration Modes and Trimming
          1. Foreground Calibration Mode
          2. Background Calibration Mode
          3. Low-Power Background Calibration (LPBG) Mode
        11. Offset Calibration
        12. Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
      2. 8.5.2 SCS
      3. 8.5.3 SCLK
      4. 8.5.4 SDI
      5. 8.5.5 SDO
      6. 8.5.6 Streaming Mode
    6. 8.6 SPI_Register_Map Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. Design Requirements
        2. Detailed Design Procedure
          1. Analog Front-End Requirements
          2. Calculating Clock and SerDes Frequencies
        3. Application Curves
        4. Quad Channel Hand-Held 1.25-GSPS 625-MSPS Oscilloscope
      2. 9.2.2 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Low-Power Background Calibration (LPBG) Mode

Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores while still allowing background calibration of the ADC cores to maintain optimal performance as operating conditions change. LPBG calibration modifies the background calibration procedure by powering down the spare ADC cores until they are ready to be calibrated. Set LP_EN = 1 to enable the low-power background calibration feature. Calibration and swapping of ADC cores can be controlled either automatically by the device or manually by the system by setting LP_TRIG appropriately. Manual control (LP_TRIG=1) allows the system to trigger calibration in order to limit the number of calibration cycles that occur to avoid unnecessary core swaps or to keep power consumption at a minimum. For instance, the user may decide to run calibration only when the system temperature changes by some fixed temperature. If manual control is not necessary the automatic calibration control can be enabled (LP_TRIG=0) to calibrate at fixed time intervals.

In automatic calibration mode (LP_TRIG=0) the spare ADC core sleep time can be controlled by the LP_SLEEP_DLY register setting. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps before waking up for calibration (when LP_EN=1 and LP_TRIG = 0). LP_WAKE_DLY sets how long the core is allowed to stabilize after being awoken before calibration begins. In automatic calibration control mode the freshly calibrated core is swapped in for an active core as soon as calibration finishes and the new spare core is powered down for the sleep duration before waking up and calibrating.

Manual calibration control is enabled by setting LP_TRIG high in order to use the calibration trigger (CAL_SOFT_TRIG or CALTRIG) to trigger calibrations and core swaps. When manual control is enabled (LP_TRIG=1) the spare ADC is held in sleep mode while the calibration trigger is high. Setting the calibration trigger low then wakes up the spare ADC core and starts the calibration routine after waiting for the specified wake delay (LP_WAKE_DLY). The spare ADC core is swapped in for an active core once calibration is complete and the calibration trigger is set high again. If the calibration trigger is held low, then the spare ADC core calibrates and powers until the calibration trigger goes high; therefore consuming power. ADC09QJ1300-Q1 can report when the spare ADC finishes calibration on the CALSTAT output pin by setting the CALSTAT pin to output the CAL_STOPPED signal (CAL_STATUS_SEL = 1). For lowest power consumption, set the calibration trigger high before calibration finishes to allow the spare ADC to swap in for an active ADC core as soon as calibration finishes. Otherwise, the ADC core swap can be timed manually by setting the calibration trigger high at the desired time to minimize system impact of potential glitches caused by the swapping procedure.

In LPBG mode there is an increase in power consumption during the ADC core calibration. The longer the spare ADC is held asleep the lower the average power consumption, however large shifts in operating conditions during the sleep cycle may cause degraded ADC performance due to non-optimized calibration data for the active ADC core. The power consumption roughly alternates between the power consumption in foreground calibration when the spare ADC core is sleeping to the power consumption in background calibration when the spare ADC is being calibrated. Design the power-supply network to handle the transient power requirements for this mode, including bulk capacitance after any power supply filtering network to help regulate the supply voltage during the supply transient.