SBAS997A February   2020  – June 2021 ADC09DJ1300-Q1 , ADC09QJ1300-Q1 , ADC09SJ1300-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Comparison
      2. 8.3.2 Analog Input
        1. Analog Input Protection
        2. Full-Scale Voltage (VFS) Adjustment
        3. Analog Input Offset Adjust
        4. ADC Core
          1. ADC Core Calibration
          2. ADC Theory of Operation
          3. Analog Reference Voltage
          4. ADC Over-range Detection
          5. Code Error Rate (CER)
        5. Temperature Monitoring Diode
        6. Timestamp
        7. Clocking
          1. Converter PLL (C-PLL) for Sampling Clock Generation
          2. LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
          3. Optional CMOS Clock Outputs (ORC, ORD)
          4. SYSREF for JESD204C Subclass-1 Deterministic Latency
            1. SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
            2. SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        8. JESD204C Interface
          1.  Transport Layer
          2.  Scrambler
          3.  Link Layer
          4.  8B/10B Link Layer
            1. Data Encoding (8B/10B)
            2. Multiframes and the Local Multiframe Clock (LMFC)
            3. Code Group Synchronization (CGS)
            4. Initial Lane Alignment Sequence (ILAS)
            5. Frame and Multiframe Monitoring
          5.  64B/66B Link Layer
            1. 64B/66B Encoding
            2. Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. Cyclic Redundancy Check (CRC) Mode
                2. Forward Error Correction (FEC) Mode
            3. Initial Lane Alignment
            4. Block, Multiblock and Extended Multiblock Alignment Monitoring
          6.  Physical Layer
            1. SerDes Pre-Emphasis
          7.  JESD204C Enable
          8.  Multi-Device Synchronization and Deterministic Latency
          9.  Operation in Subclass 0 Systems
          10. Alarm Monitoring
            1. Clock Upset Detection
            2. FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Mode and High Performance Mode
      2. 8.4.2 JESD204C Modes
        1. JESD204C Transport Layer Data Formats
        2. 64B/66B Sync Header Stream Configuration
        3. Redundant Data Mode (Alternate Lanes)
      3. 8.4.3 Power-Down Modes
      4. 8.4.4 Test Modes
        1.  Serializer Test-Mode Details
        2.  PRBS Test Modes
        3.  Clock Pattern Mode
        4.  Ramp Test Mode
        5.  Short and Long Transport Test Mode
          1. Short Transport Test Pattern
        6.  D21.5 Test Mode
        7.  K28.5 Test Mode
        8.  Repeated ILA Test Mode
        9.  Modified RPAT Test Mode
        10. Calibration Modes and Trimming
          1. Foreground Calibration Mode
          2. Background Calibration Mode
          3. Low-Power Background Calibration (LPBG) Mode
        11. Offset Calibration
        12. Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
      2. 8.5.2 SCS
      3. 8.5.3 SCLK
      4. 8.5.4 SDI
      5. 8.5.5 SDO
      6. 8.5.6 Streaming Mode
    6. 8.6 SPI_Register_Map Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. Design Requirements
        2. Detailed Design Procedure
          1. Analog Front-End Requirements
          2. Calculating Clock and SerDes Frequencies
        3. Application Curves
        4. Quad Channel Hand-Held 1.25-GSPS 625-MSPS Oscilloscope
      2. 9.2.2 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)

The SYSREF Windowing block is used to first detect the position of SYSREF relative to the input clock (CLK± or SE_CLK) rising edge and then to select a desired SYSREF sampling instance, which is a delayed version of the input clock, to maximize setup and hold timing margins. In many cases a single SYSREF sampling position (SYSREF_SEL) is sufficient to meet timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However, this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF as operating conditions change or to remove system-to-system variation at production test by finding a unique optimal value at nominal conditions for each system.

This section describes proper usage of the SYSREF Windowing block. First, apply the device clock and SYSREF to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the SYSREF_POS field. Each bit of SYSREF_POS represents a potential SYSREF sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling position has a potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the positions of SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting SYSREF_SEL to the value corresponding to that SYSREF_POS position. In general, the middle sampling position between two setup and hold instances is chosen. Ideally, SYSREF_POS and SYSREF_SEL are performed at the nominal operating conditions of the system (temperature and supply voltage) to provide maximum margin for operating condition variations. This process can be performed at final test and the optimal SYSREF_SEL setting can be stored for use at every system power up. Further, SYSREF_POS can be used to characterize the skew between CLK± and SYSREF± over operating conditions for a system by sweeping the system temperature and supply voltages. For systems that have large variations in CLK± to SYSREF± skew, this characterization can be used to track the optimal SYSREF sampling position as system operating conditions change. In general, a single value can be found that meets timing over all conditions for well-matched systems, such as those where CLK± and SYSREF± come from a single clocking device.

The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are finer. See the Recommended Operating Conditions table for delay step sizes when SYSREF_ZOOM is enabled and disabled. In general, SYSREF_ZOOM is recommended to always be used (SYSREF_ZOOM = 1) unless a transition region (defined by 1's in SYSREF_POS) is not observed, which can be the case for low clock rates. Bits 0 and 23 of SYSREF_POS are always be set to 1 because there is insufficient information to determine if these settings are close to a timing violation, although the actual valid window can extend beyond these sampling positions. The value programmed into SYSREF_SEL is the decimal number representing the desired bit location in SYSREF_POS. Table 8-7 lists some example SYSREF_POS readings and the optimal SYSREF_SEL settings. Although 24 sampling positions are provided by the SYSREF_POS status register, SYSREF_SEL only allows selection of the first 16 sampling positions, corresponding to SYSREF_POS bits 0 to 15. The additional SYSREF_POS status bits are intended only to provide additional knowledge of the SYSREF valid window. In general, lower values of SYSREF_SEL are selected because of delay variation over supply voltage, however in the fourth example a value of 15 provides additional margin and can be selected instead.

Table 8-7 Examples of SYSREF_POS Readings and SYSREF_SEL Selections
(Largest Delay)
(Smallest Delay)
b10000000b01100000b000110018 or 9
b10000000b01100000b000000016 or 7
b10000000b00000011b000000014 or 15
Red coloration indicates the bits that are selected, as given in the last column of this table.