SBAS997A February   2020  – June 2021 ADC09DJ1300-Q1 , ADC09QJ1300-Q1 , ADC09SJ1300-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Comparison
      2. 8.3.2 Analog Input
        1. 8.3.2.1 Analog Input Protection
        2. 8.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 8.3.2.3 Analog Input Offset Adjust
        4. 8.3.2.4 ADC Core
          1. 8.3.2.4.1 ADC Core Calibration
          2. 8.3.2.4.2 ADC Theory of Operation
          3. 8.3.2.4.3 Analog Reference Voltage
          4. 8.3.2.4.4 ADC Over-range Detection
          5. 8.3.2.4.5 Code Error Rate (CER)
        5. 8.3.2.5 Temperature Monitoring Diode
        6. 8.3.2.6 Timestamp
        7. 8.3.2.7 Clocking
          1. 8.3.2.7.1 Converter PLL (C-PLL) for Sampling Clock Generation
          2. 8.3.2.7.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
          3. 8.3.2.7.3 Optional CMOS Clock Outputs (ORC, ORD)
          4. 8.3.2.7.4 SYSREF for JESD204C Subclass-1 Deterministic Latency
            1. 8.3.2.7.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
            2. 8.3.2.7.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        8. 8.3.2.8 JESD204C Interface
          1. 8.3.2.8.1  Transport Layer
          2. 8.3.2.8.2  Scrambler
          3. 8.3.2.8.3  Link Layer
          4. 8.3.2.8.4  8B/10B Link Layer
            1. 8.3.2.8.4.1 Data Encoding (8B/10B)
            2. 8.3.2.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
            3. 8.3.2.8.4.3 Code Group Synchronization (CGS)
            4. 8.3.2.8.4.4 Initial Lane Alignment Sequence (ILAS)
            5. 8.3.2.8.4.5 Frame and Multiframe Monitoring
          5. 8.3.2.8.5  64B/66B Link Layer
            1. 8.3.2.8.5.1 64B/66B Encoding
            2. 8.3.2.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. 8.3.2.8.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. 8.3.2.8.5.2.1.1 Cyclic Redundancy Check (CRC) Mode
                2. 8.3.2.8.5.2.1.2 Forward Error Correction (FEC) Mode
            3. 8.3.2.8.5.3 Initial Lane Alignment
            4. 8.3.2.8.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring
          6. 8.3.2.8.6  Physical Layer
            1. 8.3.2.8.6.1 SerDes Pre-Emphasis
          7. 8.3.2.8.7  JESD204C Enable
          8. 8.3.2.8.8  Multi-Device Synchronization and Deterministic Latency
          9. 8.3.2.8.9  Operation in Subclass 0 Systems
          10. 8.3.2.8.10 Alarm Monitoring
            1. 8.3.2.8.10.1 Clock Upset Detection
            2. 8.3.2.8.10.2 FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Mode and High Performance Mode
      2. 8.4.2 JESD204C Modes
        1. 8.4.2.1 JESD204C Transport Layer Data Formats
        2. 8.4.2.2 64B/66B Sync Header Stream Configuration
        3. 8.4.2.3 Redundant Data Mode (Alternate Lanes)
      3. 8.4.3 Power-Down Modes
      4. 8.4.4 Test Modes
        1. 8.4.4.1  Serializer Test-Mode Details
        2. 8.4.4.2  PRBS Test Modes
        3. 8.4.4.3  Clock Pattern Mode
        4. 8.4.4.4  Ramp Test Mode
        5. 8.4.4.5  Short and Long Transport Test Mode
          1. 8.4.4.5.1 Short Transport Test Pattern
        6. 8.4.4.6  D21.5 Test Mode
        7. 8.4.4.7  K28.5 Test Mode
        8. 8.4.4.8  Repeated ILA Test Mode
        9. 8.4.4.9  Modified RPAT Test Mode
        10. 8.4.4.10 Calibration Modes and Trimming
          1. 8.4.4.10.1 Foreground Calibration Mode
          2. 8.4.4.10.2 Background Calibration Mode
          3. 8.4.4.10.3 Low-Power Background Calibration (LPBG) Mode
        11. 8.4.4.11 Offset Calibration
        12. 8.4.4.12 Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
      2. 8.5.2 SCS
      3. 8.5.3 SCLK
      4. 8.5.4 SDI
      5. 8.5.5 SDO
      6. 8.5.6 Streaming Mode
    6. 8.6 SPI_Register_Map Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Analog Front-End Requirements
          2. 9.2.1.2.2 Calculating Clock and SerDes Frequencies
        3. 9.2.1.3 Application Curves
        4. 9.2.1.4 Quad Channel Hand-Held 1.25-GSPS 625-MSPS Oscilloscope
      2. 9.2.2 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 9 Bit
    • Maximum sampling rate: 1.3 GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (100 MHz): 53.5 dBFS
    • ENOB (100 MHz): 8.5 Bits
    • SFDR (100 MHz): 64 dBc
    • Noise floor (–20 dBFS): –143 dBFS
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS):
    • Quad Channel: 450 mW / channel
    • Dual channel: 625 mW / channel
    • Single channel: 940 mW
  • Power supplies: 1.1 V, 1.9 V