SBAS997A February   2020  – June 2021 ADC09DJ1300-Q1 , ADC09QJ1300-Q1 , ADC09SJ1300-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Comparison
      2. 8.3.2 Analog Input
        1. Analog Input Protection
        2. Full-Scale Voltage (VFS) Adjustment
        3. Analog Input Offset Adjust
        4. ADC Core
          1. ADC Core Calibration
          2. ADC Theory of Operation
          3. Analog Reference Voltage
          4. ADC Over-range Detection
          5. Code Error Rate (CER)
        5. Temperature Monitoring Diode
        6. Timestamp
        7. Clocking
          1. Converter PLL (C-PLL) for Sampling Clock Generation
          2. LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
          3. Optional CMOS Clock Outputs (ORC, ORD)
          4. SYSREF for JESD204C Subclass-1 Deterministic Latency
            1. SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
            2. SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        8. JESD204C Interface
          1.  Transport Layer
          2.  Scrambler
          3.  Link Layer
          4.  8B/10B Link Layer
            1. Data Encoding (8B/10B)
            2. Multiframes and the Local Multiframe Clock (LMFC)
            3. Code Group Synchronization (CGS)
            4. Initial Lane Alignment Sequence (ILAS)
            5. Frame and Multiframe Monitoring
          5.  64B/66B Link Layer
            1. 64B/66B Encoding
            2. Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. Cyclic Redundancy Check (CRC) Mode
                2. Forward Error Correction (FEC) Mode
            3. Initial Lane Alignment
            4. Block, Multiblock and Extended Multiblock Alignment Monitoring
          6.  Physical Layer
            1. SerDes Pre-Emphasis
          7.  JESD204C Enable
          8.  Multi-Device Synchronization and Deterministic Latency
          9.  Operation in Subclass 0 Systems
          10. Alarm Monitoring
            1. Clock Upset Detection
            2. FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Mode and High Performance Mode
      2. 8.4.2 JESD204C Modes
        1. JESD204C Transport Layer Data Formats
        2. 64B/66B Sync Header Stream Configuration
        3. Redundant Data Mode (Alternate Lanes)
      3. 8.4.3 Power-Down Modes
      4. 8.4.4 Test Modes
        1.  Serializer Test-Mode Details
        2.  PRBS Test Modes
        3.  Clock Pattern Mode
        4.  Ramp Test Mode
        5.  Short and Long Transport Test Mode
          1. Short Transport Test Pattern
        6.  D21.5 Test Mode
        7.  K28.5 Test Mode
        8.  Repeated ILA Test Mode
        9.  Modified RPAT Test Mode
        10. Calibration Modes and Trimming
          1. Foreground Calibration Mode
          2. Background Calibration Mode
          3. Low-Power Background Calibration (LPBG) Mode
        11. Offset Calibration
        12. Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
      2. 8.5.2 SCS
      3. 8.5.3 SCLK
      4. 8.5.4 SDI
      5. 8.5.5 SDO
      6. 8.5.6 Streaming Mode
    6. 8.6 SPI_Register_Map Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. Design Requirements
        2. Detailed Design Procedure
          1. Analog Front-End Requirements
          2. Calculating Clock and SerDes Frequencies
        3. Application Curves
        4. Quad Channel Hand-Held 1.25-GSPS 625-MSPS Oscilloscope
      2. 9.2.2 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Initialization Set Up

The device and JESD204 interface require a specific startup and alignment sequence. The general order of that sequence is listed in the following steps.

  1. Tie PLL_EN high to enable the PLL or low to disable the PLL. Tie PLLREF_SE high to use the SE_CLK clock input (only valid if PLL_EN is high) or low to use CLK± clock input. Configure CLKCFG0 and CLKCFG1 pins to provide the required clocks from ORC and ORD outputs, if used.
  2. Power-up the device and wait until voltages are within the recommended supply voltage range. The PD pin must be held low during power up and at all other times when PLLREFO, ORC or ORD clock outputs are necessary for system operation, if used.
  3. Apply a stable clock signal at the desired frequency to CLK± or SE_CLK depending on the state of the PLLREF_SE input.
  4. Reset the device using SOFT_RESET.
  5. Verify device initialization is completed before continuing by reading INIT_DONE until a 1 is returned.
  6. Program the C-PLL if the PLL is enabled (PLL_EN is set high). Skip to step 7 if the C-PLL is disabled (PLL_EN is set low).
    1. Program CPLL_RESET to 1 to reset the C-PLL.
    2. Program VCO_BIAS to 0x4A to set the C-PLL VCO bias settings.
    3. Program PLL_P_DIV, PLL_V_DIV and PLL_N_DIV to set the C-PLL dividers (see Converter PLL (C-PLL)).
    4. Program VCO_CAL_EN to 1 to enable VCO trim calibration or manually write the VCO trim to VCO_FREQ_TRIM (and set VCO_CAL_EN to 0). Skip to step 6.e. if manually loading VCO_FREQ_TRIM.
    5. Program CPLL_RESET to 0 to start VCO calibration and enable the C-PLL
  7. Program JESD_EN = 0 to stop the JESD204C state machine and allow setting changes.
  8. Program CAL_EN = 0 to stop the calibration state machine and allow setting changes.
  9. Program Low Power Operating Mode, if desired, according to the Low Power Mode and High Performance Mode section.
  10. Program the desired JMODE.
  11. Program the desired KM1 value. KM1 = K–1. KM1 is only used if a JMODE is chosen that uses 8B/10B encoding.
  12. Program SYNC_SEL as needed. Choose SYNCSE single-ended input or TMSTP± differential inputs.
  13. Configure device calibration settings as desired (see the CAL_CFG0 and CAL_CFG1 registers). Select foreground or background calibration modes and offset calibration as needed.
  14. Enable the TRIGOUT± clock output and configure the TRIGOUT output mode through the TRIGOUT_CTRL register, if desired.
  15. If the C-PLL is used (PLL_EN is high) then verify that VCO calibration has finished (read VCO_CAL_DONE) and that the C-PLL is locked to the reference clock (read CPLL_LOCKED) before proceeding.
  16. Program CAL_EN = 1 to enable the calibration state machine.
  17. Enable over-range via OVR_EN and adjust settings if desired.
  18. Program JESD_EN = 1 to re-start the JESD204C state machine and allow the link to restart.
  19. Trigger a foreground calibration (if enabled) by setting CAL_SOFT_TRIG to 0 and then setting it back to 1. Alternatively, choose to use the CALTRIG pin by setting CAL_TRIG_EN to 1 and then toggling the CALTRIG pin low and then high. The CALSTAT pin and the FG_DONE register bit goes high to indicate that calibration has finished.
  20. For JMODEs that use 8B/10B encoding the JESD204C interface now operates in response to the applied SYNC signal from the receiver (64B/66B does not use SYNC).
  21. Data is valid when the JESD204C receiver finishes the initialization sequence (CGS and ILAS completes for 8B/10B modes or locks to SYNC header in 64B/66B modes) and the CALSTAT pin is high (if CAL_STATUS_SEL = 0) or FG_DONE is set to 1 to indicate that calibration is finished.