SBAS774A May   2016  – December 2016 ADC32RF80 , ADC32RF83

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance Characteristics: fS = 2949.12 MSPS
    7. 6.7  AC Performance Characteristics: fS = 2457.6 MSPS (Performance Optimized for F + A + D Band)
    8. 6.8  AC Performance Characteristics: fS = 2457.6 MSPS (Performance Optimized for F + A Band)
    9. 6.9  Digital Requirements
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Input Clock Diagram
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs
        1. 8.3.1.1 Input Clamp Circuit
      2. 8.3.2  Clock Input
      3. 8.3.3  SYSREF Input
        1. 8.3.3.1 Using SYSREF
        2. 8.3.3.2 Frequency of the SYSREF Signal
      4. 8.3.4  DDC Block
        1. 8.3.4.1 Operating Mode: Receiver
        2. 8.3.4.2 Operating Mode: Wide-Bandwidth Observation Receiver
        3. 8.3.4.3 Decimation Filters
          1. 8.3.4.3.1  Divide-by-4
          2. 8.3.4.3.2  Divide-by-6
          3. 8.3.4.3.3  Divide-by-8
          4. 8.3.4.3.4  Divide-by-9
          5. 8.3.4.3.5  Divide-by-10
          6. 8.3.4.3.6  Divide-by-12
          7. 8.3.4.3.7  Divide-by-16
          8. 8.3.4.3.8  Divide-by-18
          9. 8.3.4.3.9  Divide-by-20
          10. 8.3.4.3.10 Divide-by-24
          11. 8.3.4.3.11 Divide-by-32
          12. 8.3.4.3.12 Latency with Decimation Options
        4. 8.3.4.4 Digital Multiplexer (MUX)
        5. 8.3.4.5 Numerically-Controlled Oscillators (NCOs) and Mixers
      5. 8.3.5  NCO Switching
      6. 8.3.6  SerDes Transmitter Interface
      7. 8.3.7  Eye Diagrams
      8. 8.3.8  Alarm Outputs: Power Detectors for AGC Support
        1. 8.3.8.1 Absolute Peak Power Detector
        2. 8.3.8.2 Crossing Detector
        3. 8.3.8.3 RMS Power Detector
        4. 8.3.8.4 GPIO AGC MUX
      9. 8.3.9  Power-Down Mode
      10. 8.3.10 ADC Test Pattern
        1. 8.3.10.1 Digital Block
        2. 8.3.10.2 Transport Layer
        3. 8.3.10.3 Link Layer
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 JESD204B Interface
        1. 8.4.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2 JESD204B Frame Assembly
        3. 8.4.2.3 JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
        4. 8.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        5. 8.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        6. 8.4.2.6 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
        7. 8.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
      3. 8.4.3 Serial Interface
        1. 8.4.3.1 Serial Register Write: Analog Bank
        2. 8.4.3.2 Serial Register Readout: Analog Bank
        3. 8.4.3.3 Serial Register Write: Digital Bank
        4. 8.4.3.4 Serial Register Readout: Digital Bank
        5. 8.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages
    5. 8.5 Register Maps
      1. 8.5.1  Example Register Writes
      2. 8.5.2  Register Descriptions
        1. 8.5.2.1 General Registers
          1. 8.5.2.1.1 Register 000h (address = 000h), General Registers
          2. 8.5.2.1.2 Register 002h (address = 002h), General Registers
          3. 8.5.2.1.3 Register 003h (address = 003h), General Registers
          4. 8.5.2.1.4 Register 004h (address = 004h), General Registers
          5. 8.5.2.1.5 Register 010h (address = 010h), General Registers
          6. 8.5.2.1.6 Register 011h (address = 011h), General Registers
          7. 8.5.2.1.7 Register 012h (address = 012h), General Registers
      3. 8.5.3  Master Page (M = 0)
        1. 8.5.3.1 Register 020h (address = 020h), Master Page
        2. 8.5.3.2 Register 032h (address = 032h), Master Page
        3. 8.5.3.3 Register 039h (address = 039h), Master Page
        4. 8.5.3.4 Register 03Ch (address = 03Ch), Master Page
        5. 8.5.3.5 Register 05Ah (address = 05Ah), Master Page
        6. 8.5.3.6 Register 03Dh (address = 3Dh), Master Page
        7. 8.5.3.7 Register 057h (address = 057h), Master Page
        8. 8.5.3.8 Register 058h (address = 058h), Master Page
      4. 8.5.4  ADC Page (FFh, M = 0)
        1. 8.5.4.1 Register 03Fh (address = 03Fh), ADC Page
        2. 8.5.4.2 Register 042h (address = 042h), ADC Page
      5. 8.5.5  Digital Function Page (610000h, M = 1 for Channel A and 610100h, M = 1 for Channel B)
        1. 8.5.5.1 Register A6h (address = 0A6h), Digital Function Page
      6. 8.5.6  Offset Corr Page Channel A (610000h, M = 1)
        1. 8.5.6.1 Register 034h (address = 034h), Offset Corr Page Channel A
        2. 8.5.6.2 Register 068h (address = 068h), Offset Corr Page Channel A
      7. 8.5.7  Offset Corr Page Channel B (610000h, M = 1)
        1. 8.5.7.1 Register 068h (address = 068h), Offset Corr Page Channel B
      8. 8.5.8  Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
        1. 8.5.8.1 Register 0A6h (address = 0A6h), Digital Gain Page
      9. 8.5.9  Main Digital Page Channel A (680000h, M = 1)
        1. 8.5.9.1 Register 000h (address = 000h), Main Digital Page Channel A
        2. 8.5.9.2 Register 0A2h (address = 0A2h), Main Digital Page Channel A
      10. 8.5.10 Main Digital Page Channel B (680001h, M = 1)
        1. 8.5.10.1 Register 000h (address = 000h), Main Digital Page Channel B
        2. 8.5.10.2 Register 0A2h (address = 0A2h), Main Digital Page Channel B
      11. 8.5.11 JESD Digital Page (6900h, M = 1)
        1. 8.5.11.1  Register 001h (address = 001h), JESD Digital Page
        2. 8.5.11.2  Register 002h (address = 002h ), JESD Digital Page
        3. 8.5.11.3  Register 003h (address = 003h), JESD Digital Page
        4. 8.5.11.4  Register 004h (address = 004h), JESD Digital Page
        5. 8.5.11.5  Register 006h (address = 006h), JESD Digital Page
        6. 8.5.11.6  Register 007h (address = 007h), JESD Digital Page
        7. 8.5.11.7  Register 016h (address = 016h), JESD Digital Page
        8. 8.5.11.8  Register 017h (address = 017h), JESD Digital Page
        9. 8.5.11.9  Register 032h-035h (address = 032h-035h), JESD Digital Page
        10. 8.5.11.10 Register 036h (address = 036h), JESD Digital Page
        11. 8.5.11.11 Register 037h (address = 037h), JESD Digital Page
        12. 8.5.11.12 Register 03Ch (address = 03Ch), JESD Digital Page
        13. 8.5.11.13 Register 03Eh (address = 03Eh), JESD Digital Page
      12. 8.5.12 Decimation Filter Page
        1. 8.5.12.1  Register 000h (address = 000h), Decimation Filter Page
        2. 8.5.12.2  Register 001h (address = 001h), Decimation Filter Page
        3. 8.5.12.3  Register 002h (address = 2h), Decimation Filter Page
        4. 8.5.12.4  Register 005h (address = 005h), Decimation Filter Page
        5. 8.5.12.5  Register 006h (address = 006h), Decimation Filter Page
        6. 8.5.12.6  Register 007h (address = 007h), Decimation Filter Page
        7. 8.5.12.7  Register 008h (address = 008h), Decimation Filter Page
        8. 8.5.12.8  Register 009h (address = 009h), Decimation Filter Page
        9. 8.5.12.9  Register 00Ah (address = 00Ah), Decimation Filter Page
        10. 8.5.12.10 Register 00Bh (address = 00Bh), Decimation Filter Page
        11. 8.5.12.11 Register 00Ch (address = 00Ch), Decimation Filter Page
        12. 8.5.12.12 Register 00Dh (address = 00Dh), Decimation Filter Page
        13. 8.5.12.13 Register 00Eh (address = 00Eh), Decimation Filter Page
        14. 8.5.12.14 Register 00Fh (address = 00Fh), Decimation Filter Page
        15. 8.5.12.15 Register 010h (address = 010h), Decimation Filter Page
        16. 8.5.12.16 Register 011h (address = 011h), Decimation Filter Page
        17. 8.5.12.17 Register 014h (address = 014h), Decimation Filter Page
        18. 8.5.12.18 Register 016h (address = 016h), Decimation Filter Page
        19. 8.5.12.19 Register 01Eh (address = 01Eh), Decimation Filter Page
        20. 8.5.12.20 Register 01Fh (address = 01Fh), Decimation Filter Page
        21. 8.5.12.21 Register 033h-036h (address = 033h-036h), Decimation Filter Page
        22. 8.5.12.22 Register 037h (address = 037h), Decimation Filter Page
          1. 8.5.12.22.1 Register 038h (address = 038h), Decimation Filter Page
          2. 8.5.12.22.2 Register 039h (address = 039h), Decimation Filter Page
        23. 8.5.12.23 Register 03Ah (address = 03Ah), Decimation Filter Page
      13. 8.5.13 Power Detector Page
        1. 8.5.13.1  Register 000h (address = 000h), Power Detector Page
        2. 8.5.13.2  Register 001h-002h (address = 001h-002h), Power Detector Page
        3. 8.5.13.3  Register 003h (address = 003h), Power Detector Page
        4. 8.5.13.4  Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
        5. 8.5.13.5  Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
        6. 8.5.13.6  Register 00Dh (address = 00Dh), Power Detector Page
        7. 8.5.13.7  Register 00Eh (address = 00Eh), Power Detector Page
        8. 8.5.13.8  Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power Detector Page
        9. 8.5.13.9  Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
        10. 8.5.13.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
        11. 8.5.13.11 Register 020h (address = 020h), Power Detector Page
        12. 8.5.13.12 Register 021h (address = 021h), Power Detector Page
        13. 8.5.13.13 Register 022h-025h (address = 022h-025h), Power Detector Page
        14. 8.5.13.14 Register 027h (address = 027h), Power Detector Page
        15. 8.5.13.15 Register 02Bh (address = 02Bh), Power Detector Page
        16. 8.5.13.16 Register 032h-035h (address = 032h-035h), Power Detector Page
        17. 8.5.13.17 Register 037h (address = 037h), Power Detector Page
        18. 8.5.13.18 Register 038h (address = 038h), Power Detector Page
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
        1. 9.1.3.1 External Clock Phase Noise Consideration
      4. 9.1.4 Power Consumption in Different Modes
      5. 9.1.5 Using DC Coupling in the ADC32RF8x
        1. 9.1.5.1 Bypassing the Offset Corrector Block
          1. 9.1.5.1.1 Effect of Temperature
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range AVDD19 –0.3 2.1 V
AVDD –0.3 1.4
DVDD –0.3 1.4
Voltage applied to input pins INAP, INAM and INBP, INBM –0.3 AVDD19 + 0.3 V
CLKINP, CLKINM –0.3 AVDD + 0.6
SYSREFP, SYSREFM, SYNCBP, SYNCBM –0.3 AVDD + 0.6
SCLK, SEN, SDIN, RESET, PDN, GPIO1, GPIO2, GPIO3, GPIO4 –0.2 AVDD19 + 0.2
Voltage applied to output pins –0.3 2.2 V
Temperature Operating free-air, TA –40 85 °C
Storage, Tstg –65 150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage(2) AVDD19 1.8 1.9 2.0 V
AVDD 1.1 1.15 1.25
DVDD 1.1 1.15 1.2
Temperature Operating free-air, TA –40 85 °C
Operating junction, TJ 105(1) 125
Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
Always power up the DVDD supply (1.15 V) before the AVDD19 (1.9 V) supply. The AVDD (1.15 V) supply can come up in any order.

Thermal Information

THERMAL METRIC(1) ADC32RF80 UNIT
RMP (VQFN)
72 PINS
RθJA Junction-to-ambient thermal resistance 21.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 4.4 °C/W
RθJB Junction-to-board thermal resistance 2.0 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 2.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.2 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER CONSUMPTION(4) (Dual-Channel Operation, Both Channels A and B are Active; Divide-by-4, Complex Output Mode(3))
IAVDD19 1.9-V analog supply current fS = 2949.12 MSPS 1777 1989 mA
IAVDD 1.15-V analog supply current fS = 2949.12 MSPS 970 1103 mA
IDVDD 1.15-V digital supply current fS = 2949.12 MSPS 1785 1955 mA
PD Power dissipation fS = 2949.12 MSPS 6.54 7.07 W
Global power-down power dissipation 360 mW
ANALOG INPUTS
Resolution 14 Bits
Differential input full-scale 1.35 VPP
VIC Input common-mode voltage 1.2(5) V
RIN Input resistance Differential resistance at dc 65 Ω
CIN Input capacitance Differential capacitance at dc 2 pF
VCM common-mode voltage output 1.2 V
Analog input bandwidth
(–3-dB point)
ADC driven with 50-Ω source 3200 MHz
ISOLATION
Crosstalk isolation between channel A and channel B(1) fIN = 100 MHz 100 dBc
fIN = 900 MHz 99
fIN = 1800 MHz 95
fIN = 2700 MHz 86
fIN = 3500 MHz 85
CLOCK INPUT(2)
Input clock frequency 1.5 3 GSPS
Differential (peak-to-peak) input clock amplitude 0.5 1.5 2.5 VPP
Input clock duty cycle 45% 50% 55%
Internal clock biasing 1.0 V
Internal clock termination (differential) 100 Ω
Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel.
See Figure 79.
Full-scale signal is applied to the analog inputs of all active channels.
See the Power Consumption in Different Modes section for more details.
When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within VCM ±25 mV for best performance.

AC Performance Characteristics: fS = 2949.12 MSPS

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance(5), AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN(3) NOM MAX UNIT
SNR Signal-to-noise ratio fIN = 100 MHz, AOUT = –2 dBFS 62.6 dBFS
fIN = 900 MHz, AOUT = –2 dBFS 61.1
fIN = 1850 MHz, AOUT = –2 dBFS 55.4 58.9
fIN = 2100 MHz, AOUT = –2 dBFS 58.2
fIN = 2600 MHz, AOUT = –2 dBFS 56.8
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 54.1
NSD Noise spectral density averaged across the Nyquist zone fIN = 100 MHz, AOUT = –2 dBFS 154.3 dBFS/Hz
fIN = 900 MHz, AOUT = –2 dBFS 152.8
fIN = 1850 MHz, AOUT = –2 dBFS 147.1 150.6
fIN = 2100 MHz, AOUT = –2 dBFS 149.9
fIN = 2600 MHz, AOUT = –2 dBFS 148.5
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 145.8
Small-signal SNR fIN = 1850 MHz, AOUT = –40 dBFS 63.1 dBFS
NF(1) Noise figure fIN = 1850 MHz, AOUT = –40 dBFS 24.7 dB
SINAD Signal-to-noise and distortion ratio fIN = 100 MHz, AOUT = –2 dBFS 61.7 dBFS
fIN = 900 MHz, AOUT = –2 dBFS 60.2
fIN = 1850 MHz, AOUT = –2 dBFS 58.4
fIN = 2100 MHz, AOUT = –2 dBFS 57.6
fIN = 2600 MHz, AOUT = –2 dBFS 54.8
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 53.6
ENOB Effective number of bits fIN = 100 MHz, AOUT = –2 dBFS 10.0 Bits
fIN = 900 MHz, AOUT = –2 dBFS 9.7
fIN = 1850 MHz, AOUT = –2 dBFS 9.4
fIN = 2100 MHz, AOUT = –2 dBFS 9.3
fIN = 2600 MHz, AOUT = –2 dBFS 8.8
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 8.6
SFDR Spurious-free dynamic range fIN = 100 MHz, AOUT = –2 dBFS 68.0 dBc
fIN = 900 MHz, AOUT = –2 dBFS 66.0
fIN = 1850 MHz, AOUT = –2 dBFS 58 67.0
fIN = 2100 MHz, AOUT = –2 dBFS 64.0
fIN = 2600 MHz, AOUT = –2 dBFS 58.0
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 62.0
HD2(4) Second-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 72.0 dBc
fIN = 900 MHz, AOUT = –2 dBFS 73.0
fIN = 1850 MHz, AOUT = –2 dBFS 58 67.0
fIN = 2100 MHz, AOUT = –2 dBFS 64.0
fIN = 2700 MHz, AOUT = –2 dBFS 58.0
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 62.0
HD3 Third-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 68.0 dBc
fIN = 900 MHz, AOUT = –2 dBFS 66.0
fIN = 1850 MHz, AOUT = –2 dBFS 61 73.0
fIN = 2100 MHz, AOUT = –2 dBFS 80.0
fIN = 2600 MHz, AOUT = –2 dBFS 72.0
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 65.0
HD4, HD5 Fourth- and fifth-order harmonic distortion fIN = 100 MHz, AOUT = –2 dBFS 85.0 dBc
fIN = 900 MHz, AOUT = –2 dBFS 81.0
fIN = 1850 MHz, AOUT = –2 dBFS 61 84.0
fIN = 2100 MHz, AOUT = –2 dBFS 84.0
fIN = 2600 MHz, AOUT = –2 dBFS 80.0
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 87.0
IL spur Interleaving spurs:
fS / 2 – fIN,
fS / 4 ± fIN
fIN = 100 MHz, AOUT = –2 dBFS 90.0 dBc
fIN = 900 MHz, AOUT = –2 dBFS 77.0
fIN = 1850 MHz, AOUT = –2 dBFS 69 79.0
fIN = 2100 MHz, AOUT = –2 dBFS 76.0
fIN = 2600 MHz, AOUT = –2 dBFS 77.0
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 77.0
HD2 IL Interleaving spur for HD2:
fS / 2 – HD2
fIN = 100 MHz, AOUT = –2 dBFS 84.0 dBc
fIN = 900 MHz, AOUT = –2 dBFS 82.0
fIN = 1850 MHz, AOUT = –2 dBFS 62 80.0
fIN = 2100 MHz, AOUT = –2 dBFS 76.0
fIN = 2600 MHz, AOUT = –2 dBFS 65.0
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 77.0
Worst spur Spurious-free dynamic range (excluding HD2, HD3, HD4, HD5, and interleaving spurs IL and HD2 IL) fIN = 100 MHz, AOUT = –2 dBFS 80.0 dBc
fIN = 900 MHz, AOUT = –2 dBFS 76.0
fIN = 1850 MHz, AOUT = –2 dBFS 64 76.0
fIN = 2100 MHz, AOUT = –2 dBFS 75.0
fIN = 2600 MHz, AOUT = –2 dBFS 75.0
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain 71.0
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 1770 MHz, fIN2 = 1790 MHz,
AOUT = –8 dBFS (each tone)
70 dBFS
fIN1 = 1800 MHz, fIN2 = 2600 MHz,
AOUT = –8 dBFS (each tone)
73
fIN1 = 3490 MHz, fIN2 = 3510 MHz,
AOUT = –8 dBFS (each tone) with 2-dB gain
67
The ADC internal resistance = 65 Ω, the driving source resistance = 50 Ω.
Output amplitude, AOUT, refers to the signal amplitude in the ADC digital output that is same as the analog input amplitude, AIN, except when the digital gain feature is used. If digital gain is G, then AOUT = G + AIN.
Minimum values are specified at AOUT = –3 dBFS.
The minimum value of HD2 is specified by bench characterization.
Performance is shown with DDC bypassed. When DDC is enabled, performance improves by the decimation filtering process.

AC Performance Characteristics: fS = 2457.6 MSPS
(Performance Optimized for F + A + D Band(1))

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
SNR Signal-to-noise ratio fIN = 1850 MHz, AOUT = –2 dBFS 58.5 dBFS
fIN = 2600 MHz, AOUT = –2 dBFS 55.8
SFDR Spurious-free dynamic range fIN = 1850 MHz, AOUT = –2 dBFS 60.0 dBc
fIN = 2600 MHz, AOUT = –2 dBFS 57.0
HD2 Second-order harmonic distortion fIN = 1850 MHz, AOUT = –2 dBFS 59.0 dBc
fIN = 2600 MHz, AOUT = –2 dBFS 57.0
HD3 Third-order harmonic distortion fIN = 1850 MHz, AOUT = –2 dBFS 75.0 dBc
fIN = 2600 MHz, AOUT = –2 dBFS 65.0
IL spur Interleaving spurs:
fS / 2 – fIN,
fS / 4 ± fIN
fIN = 1850 MHz, AOUT = –2 dBFS 84.0 dBc
fIN = 2600 MHz, AOUT = –2 dBFS 76.0
HD2 IL Interleaving spur for HD2:
fS / 2 – HD2
fIN = 1850 MHz, AOUT = –2 dBFS 76.0 dBc
fIN = 2600 MHz, AOUT = –2 dBFS 67.0
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 1800 MHz, fIN2 = 2600 MHz,
AOUT = –8 dBFS (each tone)
67.0 dBFS
F-band = 1880 MHz to 1920 MHz, A-band = 2010 MHz to 2025 MHz, and D-band = 2570 MHz to 2620 MHz.

AC Performance Characteristics: fS = 2457.6 MSPS
(Performance Optimized for F + A Band(1))

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
SNR Signal-to-noise ratio fIN = 1850 MHz, AOUT = –2 dBFS 58.7 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS 57.9
SFDR Spurious-free dynamic range fIN = 1850 MHz, AOUT = –2 dBFS 71.0 dBc
fIN = 2100 MHz, AOUT = –2 dBFS 69.0
HD2 Second-order harmonic distortion fIN = 1850 MHz, AOUT = –2 dBFS 71.0 dBc
fIN = 2100 MHz, AOUT = –2 dBFS 69.0
HD3 Third-order harmonic distortion fIN = 1850 MHz, AOUT = –2 dBFS 75.0 dBc
fIN = 2100 MHz, AOUT = –2 dBFS 76.0
IL spur Interleaving spurs:
fS / 2 – fIN,
fS / 4 ± fIN
fIN = 1850 MHz, AOUT = –2 dBFS 82.0 dBc
fIN = 2100 MHz, AOUT = –2 dBFS 84.0
HD2 IL Interleaving spur for HD2:
fS / 2 – HD2
fIN = 1850 MHz, AOUT = –2 dBFS 80.0 dBc
fIN = 2100 MHz, AOUT = –2 dBFS 80.0
F-band = 1880 MHz to 1920 MHz, A-band = 2010 MHz to 2025 MHz, and D-band = 2570 MHz to 2620 MHz.

Digital Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, GPIO1, GPIO2, GPIO3, GPIO4)
VIH High-level input voltage 0.8 V
VIL Low-level input voltage 0.4 V
IIH High-level input current 50 µA
IIL Low-level input current –50 µA
Ci Input capacitance 4 pF
DIGITAL OUTPUTS (SDOUT, GPIO1, GPIO2, GPIO3, GPIO4)
VOH High-level output voltage AVDD19–0.1 AVDD19 V
VOL Low-level output voltage 0.1 V
DIGITAL INPUTS (SYSREFP and SYSREFM; SYNCBP and SYNCBM; Requires External Biasing)
VID Differential input voltage 350 450 800 mVPP
VCM Input common-mode voltage 1.05 1.2 1.325 V
DIGITAL OUTPUTS (JESD204B Interface: DA[3:0], DB[3:0], Meets JESD204B LV-0IF-11G-SR Standard)
|VOD| Output differential voltage 700 mVPP
|VOCM| Output common-mode voltage 450 mV
Transmitter short-circuit current Transmitter pins shorted to any voltage between –0.25 V and 1.45 V –100 100 mA
zos Single-ended output impedance 50 Ω
Co Output capacitance Output capacitance inside the device, from either output to ground 2 pF

Timing Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
MIN NOM MAX UNIT
SAMPLE TIMING
Aperture delay 250 750 ps
Aperture delay matching between two channels on the same device ±15 ps
Aperture delay matching between two devices at the same
temperature and supply voltage
±150 ps
Aperture jitter, clock amplitude = 2 VPP 90 fS
Latency
(1)(3)
Data latency, ADC sample to digital output DDC block bypassed(4), LMFS = 8224 424 Input clock cycles
Fast overrange latency, ADC sample to FOVR indication on GPIO pins 70
tPD Propagation delay time: logic gates and output buffer delay
(does not change with fS)
6 ns
SYSREF TIMING(2)
tSU_SYSREF SYSREF setup time: referenced to clock rising edge, 2949.12 MSPS 140 70 ps
tH_SYSREF SYSREF hold time: referenced to clock rising edge, 2949.12 MSPS 50 20 ps
Valid transition window sampling period: tSU_SYSREF – tH_SYSREF, 2949.12 MSPS 143 ps
JESD OUTPUT INTERFACE TIMING
UI Unit interval: 12.5 Gbps 80 100 400 ps
Serial output data rate 2.5 10.0 12.5 Gbps
Rise, fall times: 1-pF, single-ended load capacitance to ground 60 ps
Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps 25 %UI
Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps 0.99 %UI, rms
Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps 9.1 %UI, pk-pk
Overall latency = latency + tPD.
Common-mode voltage for the SYSREF input is kept at 1.2 V.
Latency increases when the DDC modes are used; see Table 5.
For latency in different DDC options, see .
ADC32RF80 ADC32RF83 digital_inpt_outpts_sbas747.gif
VOCM is not the same as VICM. Similarly, VOD is not the same as VID.
Figure 1. Logic Levels for Digital Inputs and Outputs
ADC32RF80 ADC32RF83 tmg_rqrmnts_dgm_sbas747.gif Figure 2. SYSREF Timing Diagram

Typical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
ADC32RF80 ADC32RF83 D001_SBAS774.gif
SNR = 62.2 dBFS; SFDR = 68 dBc;
HD2 = –68 dBc; HD3 = –73 dBc; non HD2, HD3 = 77 dBc;
IL spur = 86 dBc; fIN = 100 MHz
Figure 3. FFT for 100-MHz Input Frequency
ADC32RF80 ADC32RF83 D002_SBAS774.gif
SNR = 61.2 dBFS; SFDR = 66 dBc;
HD2 = –77 dBc; HD3 = –66 dBc; non HD2, HD3 = 80 dBc;
IL spur = 83 dBc; fIN = 900 MHz
Figure 5. FFT for 900-MHz Input Signal
ADC32RF80 ADC32RF83 D003_SBAS774.gif
SNR = 59.1 dBFS; SFDR = 65 dBc;
HD2 = –65 dBc; HD3 = –73 dBc; non HD2, HD3 = 73 dBc;
IL spur = 76 dBc; fIN = 1.7 GHz
Figure 7. FFT for 1780-MHz Input Signal
ADC32RF80 ADC32RF83 D004_SBAS774.gif
SNR = 58.2 dBFS; SFDR = 64 dBc;
HD2 = –64 dBc; HD3 = –85 dBc; non HD2, HD3 = 73 dBc;
IL spur = 74 dBc; fIN = 2.1 GHz
Figure 9. FFT for 2100-MHz Input Signal
ADC32RF80 ADC32RF83 D005_SBAS774.gif
SNR = 56.9 dBFS; SFDR = 62 dBc;
HD2 = –62 dBc; HD3 = –72 dBc; non HD2, HD3 = 72 dBc;
IL spur = 64 dBc; fIN = 2.6 GHz
Figure 11. FFT for 2600-MHz Input Signal
ADC32RF80 ADC32RF83 D006_SBAS774.gif
SNR = 54.2 dBFS; SFDR = 60 dBc;
HD2 = –60 dBc; HD3 = –64 dBc; non HD2, HD3 = 71 dBc;
IL spur = 80 dBc; fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB gain
Figure 13. FFT for 3500-MHz Input Signal
ADC32RF80 ADC32RF83 D073_SBAS774.gif
fIN1 = 900 MHz, fIN2 = 950 MHz, AIN = –8 dBFS, IMD = 79 dBFS
Figure 15. FFT for Two-Tone Input Signal (–8 dBFS)
ADC32RF80 ADC32RF83 D075_SBAS774.gif
fIN1 = 900 MHz, fIN2 = 950 MHz, AIN = –8 dBFS, IMD = 75 dBFS
Figure 17. FFT for Two-Tone Input Signal
(–8 dBFS, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D007_SBAS774.gif
fIN1 = 1.77 GHz, fIN2 = 1.79 GHz, AIN = –8 dBFS, IMD = 70 dBFS
Figure 19. FFT for Two-Tone Input Signal (–8 dBFS)
ADC32RF80 ADC32RF83 D061_SBAS774.gif
fIN1 = 1.77 GHz, fIN2 = 1.79 GHz, AIN = –8 dBFS,
IMD = 76 dBFS
Figure 21. FFT for Two-Tone Input Signal
(–8 dBFS, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D009_SBAS774.gif
fIN1 = 1.8 MHz, fIN2 = 2.6 GHz, AIN = –8 dBFS, IMD = 71 dBFS
Figure 23. FFT for Two-Tone Input Signal (–8 dBFS)
ADC32RF80 ADC32RF83 D063_SBAS774.gif
fIN1 = 2.09 GHz, fIN2 = 2.1 GHz, AIN = –8 dBFS, IMD = 76 dBFS
Figure 25. FFT for Two-Tone Input Signal
(–8 dBFS, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D011_SBAS774.gif
fIN1 = 3.49 MHz, fIN2 = 3.51 GHz, IMD = 66 dBFS,
AIN = –3 dBFS with 2-dB gain
Figure 27. FFT for Two-Tone Input Signal (–8 dBFS)
ADC32RF80 ADC32RF83 D065_SBAS774.gif
fIN1 = 2.59 GHz, fIN2 = 2.6 GHz, AIN = –8 dBFS, IMD = 65 dBFS
Figure 29. FFT for Two-Tone Input Signal
(–8 dBFS, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D013_SBAS774.gif
fIN1 = 1.77 GHz, fIN2 = 1.79 GHz
Figure 31. Intermodulation Distortion vs Input Amplitude (1770 MHz and 1790 MHz)
ADC32RF80 ADC32RF83 D014_SBAS774.gif
fIN1 = 1.8 GHz, fIN2 = 2.6 GHz, AIN = –36 dBFS
Figure 33. Intermodulation Distortion vs Input Amplitude (1800 MHz and 2600 MHz)
ADC32RF80 ADC32RF83 D015_SBAS774.gif
fIN1 = 3.49 GHz, fIN2 = 3.51 GHz with 2-dB digital gain
Figure 35. Intermodulation Distortion vs Input Amplitude (3490 MHz and 3510 MHz)
ADC32RF80 ADC32RF83 D016_SBAS774.gif
AOUT = –2 dBFS with 0-dB gain for fIN less than 3 GHz,
AOUT = –3 dBFS with 2-dB gain for fIN more than 3 GHz
Figure 37. Spurious-Free Dynamic Range vs
Input Frequency
ADC32RF80 ADC32RF83 D017_SBAS774.gif
AOUT = –2 dBFS with 0-dB gain for fIN less than 3 GHz,
AOUT = –3 dBFS with 2-dB gain for fIN more than 3 GHz
Figure 39. IL Spur vs Input Frequency
ADC32RF80 ADC32RF83 D018_SBAS774.gif
AOUT = –2 dBFS with 0-dB gain for fIN less than 3 GHz,
AOUT = –3 dBFS with 2-dB gain for fIN more than 3 GHz
Figure 41. Signal-to-Noise Ratio vs Input Frequency
ADC32RF80 ADC32RF83 D019_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS
Figure 43. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC32RF80 ADC32RF83 D021_SBAS774.gif
fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB digital gain
Figure 45. Signal-to-Noise Ratio vs
AVDD Supply and Temperature
ADC32RF80 ADC32RF83 D023_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS
Figure 47. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC32RF80 ADC32RF83 D025_SBAS774.gif
fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB digital gain
Figure 49. Signal-to-Noise Ratio vs
DVDD Supply and Temperature
ADC32RF80 ADC32RF83 D027_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS
Figure 51. Signal-to-Noise Ratio vs
AVDD19 Supply and Temperature
ADC32RF80 ADC32RF83 D029_SBAS774.gif
fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB digital gain
Figure 53. Signal-to-Noise Ratio vs
AVDD19 Supply and Temperature
ADC32RF80 ADC32RF83 D031_SBAS774.gif
fIN = 1.78 GHz
Figure 55. HD2 Histogram at AVDD19 = 1.8 V
ADC32RF80 ADC32RF83 D033_SBAS774.gif
fIN = 1.78 GHz
Figure 57. HD2 Histogram at AVDD19 = 2.0 V
ADC32RF80 ADC32RF83 D035_SBAS774.gif
fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB digital gain
Figure 59. Performance vs Amplitude
ADC32RF80 ADC32RF83 D037_SBAS774.gif
fIN = 3.5 GHz, AIN = –3 dBFS
Figure 61. Performance vs Clock Amplitude
ADC32RF80 ADC32RF83 D039_SBAS774.gif
fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB digital gain
Figure 63. Performance vs Clock Duty Cycle
ADC32RF80 ADC32RF83 D041_SBAS774.gif
Figure 65. Power-Supply Rejection Ratio vs
Tone Frequency
ADC32RF80 ADC32RF83 D043_SBAS774.gif
fIN = 1.8 GHz, AOUT = –2 dBFS
Figure 67. Common-Mode Rejection Ratio vs
Tone Frequency
ADC32RF80 ADC32RF83 D045_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 61.6 dBFS, SFDR (includes IL) = 82 dBc
Figure 69. FFT in 6X Decimation (Complex Output)
ADC32RF80 ADC32RF83 D047_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 63 dBFS, SFDR (includes IL) = 82 dBc
Figure 71. FFT in 9X Decimation (Complex Output)
ADC32RF80 ADC32RF83 D049_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 63.7 dBFS, SFDR (includes IL) = 83 dBc
Figure 73. FFT in 12X Decimation (Complex Output)
ADC32RF80 ADC32RF83 D051_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 64 dBFS, SFDR (includes IL) = 83 dBc
Figure 75. FFT in 18X Decimation (Complex Output)
ADC32RF80 ADC32RF83 D053_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 64.4 dBFS, SFDR (includes IL) = 82 dBc
Figure 77. FFT in 24X Decimation (Complex Output)
ADC32RF80 ADC32RF83 D055_SBAS774.gif
SNR = 62.4 dBFS; SFDR = 71 dBc;
HD2 = –71 dBc; HD3 = –83 dBc; non HD2, HD3 = 82 dBc;
IL spur = 80 dBc; fIN = 100 MHz
Figure 4. FFT for 100-MHz Input Signal (fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D056_SBAS774.gif
SNR = 62.1 dBFS; SFDR = 76 dBc;
HD2 = –76 dBc; HD3 = –83 dBc; non HD2, HD3 = 82 dBc;
IL spur = 83 dBc; fIN = 900 MHz
Figure 6. FFT for 900-MHz Input Signal (fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D057_SBAS774.gif
SNR = 58 dBFS; SFDR = 69 dBc;
HD2 = –69 dBc; HD3 = –75 dBc; non HD2, HD3 = 74 dBc;
IL spur = 78 dBc; fIN = 1.85 GHz
Figure 8. FFT for 1850-MHz Input Signal (fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D058_SBAS774.gif
SNR = 57.5 dBFS; SFDR = 70 dBc;
HD2 = –70 dBc; HD3 = –81 dBc; non HD2, HD3 = 75 dBc;
IL spur = 77 dBc; fIN = 2.1 GHz
Figure 10. FFT for 2100-MHz Input Signal (fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D059_SBAS774.gif
SNR = 55.4 dBFS; SFDR = 60 dBc;
HD2 = –60 dBc; HD3 = –67 dBc; non HD2, HD3 = 72 dBc;
IL spur = 75 dBc; fIN = 2.6 GHz
Figure 12. FFT for 2600-MHz Input Signal (fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D060_SBAS774.gif
SNR = 53.6 dBFS; SFDR = 47 dBc;
HD2 = –50 dBc; HD3 = –47 dBc; non HD2, HD3 = 70 dBc;
IL spur = 67 dBc; fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB gain
Figure 14. FFT for 3500-MHz Input Signal (fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D074_SBAS774.gif
fIN1 = 900 MHz, fIN2 = 950 MHz, AIN = –36 dBFS, IMD = 97 dBFS
Figure 16. FFT for Two-Tone Input Signal (–36 dBFS)
ADC32RF80 ADC32RF83 D076_SBAS774.gif
fIN1 = 900 MHz, fIN2 = 950 MHz, AIN = –36 dBFS,
IMD = 92 dBFS
Figure 18. FFT for Two-Tone Input Signal
(–36 dBFS, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D008_SBAS774.gif
fIN1 = 1.77 GHz, fIN2 = 1.790 GHz, AIN = –36 dBFS,
IMD = 97 dBFS
Figure 20. FFT for Two-Tone Input Signal (–36 dBFS)
ADC32RF80 ADC32RF83 D062_SBAS774.gif
fIN1 = 1.77 GHz, fIN2 = 1.790 GHz, AIN = –36 dBFS,
IMD = 96 dBFS
Figure 22. FFT for Two-Tone Input Signal
(–36 dBFS, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D010_SBAS774.gif
fIN1 = 1.8 GHz, fIN2 = 2.6 GHz, AIN = –36 dBFS, IMD = 94 dBFS
Figure 24. FFT for Two-Tone Input Signal
ADC32RF80 ADC32RF83 D064_SBAS774.gif
fIN1 = 2.09 MHz, fIN2 = 2.1 GHz, AIN = –36 dBFS,
IMD = 94 dBFS
Figure 26. FFT for Two-Tone Input Signal
(–36 dBFS, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D012_SBAS774.gif
fIN1 = 3.49 GHz, fIN2 = 3.51 GHz, IMD = 92 dBFS,
AIN = –3 dBFS with 2-dB gain
Figure 28. FFT for Two-Tone Input Signal (–36 dBFS)
ADC32RF80 ADC32RF83 D066_SBAS774.gif
fIN1 = 2.59 GHz, fIN2 = 2.6 GHz, AIN = –36 dBFS,
IMD = 92 dBFS
Figure 30. FFT for Two-Tone Input Signal
(–36 dBFS, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D067_SBAS774.gif
fIN1 = 1.77 GHz, fIN2 = 1.79 GHz
Figure 32. Intermodulation Distortion vs Input Amplitude (1770 MHz and 1790 MHz, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D068_SBAS774.gif
fIN1 = 2.09 GHz, fIN2 = 2.1 GHz
Figure 34. Intermodulation Distortion vs Input Amplitude (1800 MHz and 2600 MHz, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D069_SBAS774.gif
fIN1 = 2.59GHz, fIN2 = 2.6 GHz
Figure 36. Intermodulation Distortion vs Input Amplitude (3490 MHz and 3510 MHz, fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D070_SBAS774.gif
AOUT = –2 dBFS with 0-dB gain for fIN less than 3 GHz,
AOUT = –3 dBFS with 2-dB gain for fIN more than 3 GHz
Figure 38. Spurious-Free Dynamic Range vs
Input Frequency (fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D071_SBAS774.gif
AOUT = –2 dBFS with 0-dB gain for fIN less than 3 GHz,
AOUT = –3 dBFS with 2-dB gain for fIN more than 3 GHz
Figure 40. IL Spur vs Input Frequency (fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D072_SBAS774.gif
AOUT = –2 dBFS with 0-dB gain for fIN less than 3 GHz,
AOUT = –3 dBFS with 2-dB gain for fIN more than 3 GHz
Figure 42. Signal-to-Noise Ratio vs Input Frequency
(fS = 2457.6 MSPS)
ADC32RF80 ADC32RF83 D020_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS
Figure 44. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC32RF80 ADC32RF83 D022_SBAS774.gif
fIN = 3.5GHz, AIN = –3 dBFS with 2-dB digital gain
Figure 46. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature
ADC32RF80 ADC32RF83 D024_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS
Figure 48. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC32RF80 ADC32RF83 D026_SBAS774.gif
fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB digital gain
Figure 50. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature
ADC32RF80 ADC32RF83 D028_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS
Figure 52. Spurious-Free Dynamic Range vs
AVDD19 Supply and Temperature
ADC32RF80 ADC32RF83 D030_SBAS774.gif
fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB digital gain
Figure 54. Spurious-Free Dynamic Range vs
AVDD19 Supply and Temperature
ADC32RF80 ADC32RF83 D032_SBAS774.gif
fIN = 1.78 GHz
Figure 56. HD2 Histogram at AVDD19 = 1.9 V
ADC32RF80 ADC32RF83 D034_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS
Figure 58. Performance vs Amplitude
ADC32RF80 ADC32RF83 D036_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS
Figure 60. Performance vs Clock Amplitude
ADC32RF80 ADC32RF83 D038_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS
Figure 62. Performance vs Clock Duty Cycle
ADC32RF80 ADC32RF83 D040_SBAS774.gif
fIN = 3.5 GHz, AIN = –3 dBFS, PSRR = 37 dB,
fPSRR = 3 MHz, APSRR = 50 mVPP, AVDD = 1.9 V
Figure 64. Power-Supply Rejection Ratio FFT for
Test Signal on AVDD Supply
ADC32RF80 ADC32RF83 D042_SBAS774.gif
CMRR = 32 dB, fCMRR = 32 dB, APSRR = 50 mVPP
Figure 66. Common-Mode Rejection Ratio FFT
ADC32RF80 ADC32RF83 D044_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 60.6 dBFS, SFDR (includes IL) = 75 dBc
Figure 68. FFT in 4X Decimation (Complex Output)
ADC32RF80 ADC32RF83 D046_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 62.6 dBFS, SFDR (includes IL) = 86 dBc
Figure 70. FFT in 8X Decimation (Complex Output)
ADC32RF80 ADC32RF83 D048_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 63.3 dBFS, SFDR (includes IL) = 81 dBc
Figure 72. FFT in 10X Decimation (Complex Output)
ADC32RF80 ADC32RF83 D050_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 63.9 dBFS, SFDR (includes IL) = 83 dBc
Figure 74. FFT in 16X Decimation (Complex Output)
ADC32RF80 ADC32RF83 D052_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 64.4 dBFS, SFDR (includes IL) = 84 dBc
Figure 76. FFT in 20X Decimation (Complex Output)
ADC32RF80 ADC32RF83 D054_SBAS774.gif
fIN = 1.78 GHz, AIN = –2 dBFS, fS = 2949.12 MSPS,
SNR = 64.5 dBFS, SFDR (includes IL) = 79 dBc
Figure 78. FFT in 32X Decimation (Complex Output)