SBASAP7A December   2024  – April 2025 ADC3664-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter
          2. 7.3.1.2.2 AC Coupling
          3. 7.3.1.2.3 DC Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Differential Vs Single-ended Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference
      4. 7.3.4 Digital Data Path & Interface
        1. 7.3.4.1 Data Path Overview
        2. 7.3.4.2 Digital Interface
        3. 7.3.4.3 DCLKIN
        4. 7.3.4.4 Output Scrambler
        5. 7.3.4.5 Output Bit Mapper
          1. 7.3.4.5.1 2-Wire Mode
          2. 7.3.4.5.2 1-Wire Mode
          3. 7.3.4.5.3 1/2-Wire Mode
        6. 7.3.4.6 Output Data Format
        7. 7.3.4.7 Test Pattern
      5. 7.3.5 Digital Down Converter
        1. 7.3.5.1 Decimation Operation
        2. 7.3.5.2 Numerically Controlled Oscillator (NCO)
        3. 7.3.5.3 Decimation Filters
        4. 7.3.5.4 SYNC
        5. 7.3.5.5 Output Data Format with Decimation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Averaging Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Control
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
      3. 7.5.3 Device Configuration Steps
      4. 7.5.4 Register Map
        1. 7.5.4.1 Detailed Register Description
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.3 Device Configuration Steps

The following sequence summarizes all the relevant registers for changing the ADC3664-SP modes including the digital signal processing (DSP) features and the output interface. Steps 1 and 2 must come first since the E-Fuse load resets some of the device registers, the remaining steps can come in any order.

Table 7-7 Configuration Steps for the ADC3664-SP
STEPFEATUREADDRESSDESCRIPTION
1Output Interface0x07Select the output interface mode based on output resolution.
Output Resolution2-wire1-wire1/2-wire
14-bit0x2B0x6C0x8D
16-bit0x4B
18-bit0x2B
20-bit0x4B
20x13Load the output interface bit mapping using the E-fuse loader (D0 of 0x13). Write 0x01 to 0x13, wait ~ 1ms so that the bit mapping is loaded properly, and write 0x00 to 0x13.
30x19Configure the FCLK settings based on the desired device modes and interface modes.
ModeInterface ModeFCLK_SRCFCLK_DIVTOG_FCLK
DSP Features Disabled/Real Decimation2-wire010
1-wire000
1/2-wire000
Complex Decimation2-wire100
1-wire100
1/2-wire001
40x1BSelect the output interface resolution.
50x20
0x21
0x22		Configure the FCLK pattern based on device modes.
ModeOutput Resolution2-wire1-wire1/2-wire
DSP Features Disabled/Real Decimation14-bit0xFFC000xFE0000xFFC00
16-bit0xFF000
18-bit0xFF800
20-bit0xFFC00
Complex Decimation14-bit0xFFFFF0xFFFFF
16-bit
18-bit
20-bit
60x39..0x60
0x61..0x88		Change output bit mapping from the default as needed (for example, if enabling the scrambler).
70x24
0x22		Optionally, the scrambler can be enabled if the device is configured in the 2-wire interface mode.
8Digital Down converters0x24Optionally, enable the DDCs.
90x25If using the DDCs, configure the DDCs settings.
100x2A/B/C/D
0x31/2/3/4		If using complex decimation, program the desired NCO frequency.
110x27
0x2E		Set both bits to 0 if not using complex decimation.
Interface ModeIQ_ORDERQ_DEL
2-wire10
1-wire01
1/2-wire11
120x26Set the DDC gain and toggle the NCO reset bit to update the NCO frequency.