SBAS872 December 2020 ADC3683
The ADC368x includes an optional on-chip digital down conversion (DDC) decimation filter that can be enabled via SPI register settings. It supports complex decimation by 2, 4, 8, 16 and 32 using a digital mixer and a 32-bit numerically controlled oscillator (NCO) as shown in Figure 8-19.
Furthermore it supports a mode with real decimation where the complex mixer is bypassed (NCO should be set to 0 for lowest power consumption) and the digital filter acts as a low pass filter.
Internally the decimation filter calculations are performed with a 20-bit resolution in order to avoid any SNR degradation due to quantization noise limitation. The Section 184.108.40.206 truncates to the selected resolution prior to outputting the data on the digital interface.