The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more samples of the internal modulator are averaged to yield one conversion result. In applications where power consumption is critical, the improved noise performance at low data rates may not be required. For these applications, the ADS101x-Q1 support duty cycling that yield significant power savings by periodically requesting high data rate readings at an effectively lower data rate. For example, an ADS101x-Q1 in power-down state with a data rate set to 3300 SPS can be operated by a microcontroller that instructs a single-shot conversion every 7.8 ms (128 SPS). A conversion at 3300 SPS only requires approximately 0.3 ms, so the ADS101x-Q1 enter power-down state for the remaining 7.5 ms. In this configuration, the ADS101x-Q1 consume approximately 1/25th the power that is otherwise consumed in continuous-conversion mode. The duty cycling rate is completely arbitrary and is defined by the master controller. The ADS101x-Q1 offer lower data rates that do not implement duty cycling and also offer improved noise performance if required.