SBAS683B August   2014  – May 2020 ADS1120-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Multiplexer
      2. 8.3.2  Low-Noise PGA
        1. 8.3.2.1 PGA Common-Mode Voltage Requirements
        2. 8.3.2.2 Bypassing the PGA
      3. 8.3.3  Modulator
      4. 8.3.4  Digital Filter
      5. 8.3.5  Output Data Rate
      6. 8.3.6  Voltage Reference
      7. 8.3.7  Clock Source
      8. 8.3.8  Excitation Current Sources
      9. 8.3.9  Low-Side Power Switch
      10. 8.3.10 Sensor Detection
      11. 8.3.11 System Monitor
      12. 8.3.12 Offset Calibration
      13. 8.3.13 Power Supplies
      14. 8.3.14 Temperature Sensor
        1. 8.3.14.1 Converting from Temperature to Digital Codes
          1. 8.3.14.1.1 For Positive Temperatures (for Example, 50°C):
          2. 8.3.14.1.2 For Negative Temperatures (for Example, –25°C):
        2. 8.3.14.2 Converting from Digital Codes to Temperature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
      2. 8.4.2 Conversion Modes
        1. 8.4.2.1 Single-Shot Mode
        2. 8.4.2.2 Continuous-Conversion Mode
      3. 8.4.3 Operating Modes
        1. 8.4.3.1 Normal Mode
        2. 8.4.3.2 Duty-Cycle Mode
        3. 8.4.3.3 Turbo Mode
        4. 8.4.3.4 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready (DRDY)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 8.5.1.6 SPI Timeout
      2. 8.5.2 Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 RESET (0000 011x)
        2. 8.5.3.2 START/SYNC (0000 100x)
        3. 8.5.3.3 POWERDOWN (0000 001x)
        4. 8.5.3.4 RDATA (0001 xxxx)
        5. 8.5.3.5 RREG (0010 rrnn)
        6. 8.5.3.6 WREG (0100 rrnn)
      4. 8.5.4 Reading Data
      5. 8.5.5 Sending Commands
      6. 8.5.6 Interfacing with Multiple Devices
    6. 8.6 Register Map
      1. 8.6.1 Configuration Registers
        1. 8.6.1.1 Configuration Register 0 (Address = 00h) [reset = 00h]
          1. Table 12. Configuration Register 0 Field Descriptions
        2. 8.6.1.2 Configuration Register 1 (Address = 01h) [reset = 00h]
          1. Table 13. Configuration Register 1 Field Descriptions
        3. 8.6.1.3 Configuration Register 2 (Address = 02h) [reset = 00h]
          1. Table 15. Configuration Register 2 Field Descriptions
        4. 8.6.1.4 Configuration Register 3 (Address = 03h) [reset = 00h]
          1. Table 16. Configuration Register 3 Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Analog Input Filtering
      3. 9.1.3 External Reference and Ratiometric Measurements
      4. 9.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 9.1.5 Unused Inputs and Outputs
      6. 9.1.6 Pseudo Code Example
    2. 9.2 Typical Applications
      1. 9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 3-Wire RTD Measurement (–200°C to +850°C)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Bridge Measurement
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Ramp Rate
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, DR = 20 SPS, and external VREF = 2.5 V (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Absolute input current See the Typical Characteristics
Differential input current See the Typical Characteristics
SYSTEM PERFORMANCE
Resolution (no missing codes) 16 Bits
DR Data rate Normal mode 20, 45, 90, 175, 330, 600, 1000 SPS
Duty-cycle mode 5, 11.25, 22.5, 44, 82.5, 150, 250
Turbo mode 40, 90, 180, 350, 660, 1200, 2000
Noise (input-referred) See the Noise Performance section
INL Integral nonlinearity Gain = 1, VCM = 0.5 AVDD, best fit(2) 8 20 ppm
Gain = 2 to 128, VCM = 0.5 AVDD, best fit 8
VIO Input offset voltage PGA disabled, gain = 1 to 4,
differential inputs 		±4 µV
Gain = 1 to 128, differential inputs ±4
Offset drift PGA disabled, gain = 1 to 4 0.25 µV/°C
Gain = 1 to 128 0.25
Gain error PGA disabled, gain = 1 to 4 ±0.015%
Gain = 1 to 128, TA = 25°C –0.1% ±0.015% 0.1%
Gain drift PGA disabled, gain = 1 to 4 1 ppm/°C
Gain = 1 to 128(2) 1 5
NMRR Normal-mode rejection ratio(2) 50 Hz ±3%, DR = 20 SPS, external CLK, 50/60 bit = 10 105 dB
60 Hz ±3%, DR = 20 SPS, external CLK, 50/60 bit = 11 105
50 Hz or 60 Hz ±3%, DR = 20 SPS, external CLK, 50/60 bit = 01 90
CMRR Common-mode rejection ratio At dc, gain = 1 90 105 dB
f(CM) = 50 Hz, DR = 2000 SPS(2) 90 115
f(CM) = 60 Hz, DR = 2000 SPS(2) 90 115
PSRR Power-supply rejection ratio AVDD at dc, VCM = 0.5 AVDD, gain = 1 80 105 dB
DVDD at dc, VCM = 0.5 AVDD, gain = 1(2) 90 115
INTERNAL VOLTAGE REFERENCE
Initial accuracy TA = 25°C 2.045 2.048 2.051 V
Reference drift(2) 5 40 ppm/°C
Long-term drift 1000 hours 110 ppm
VOLTAGE REFERENCE INPUTS
Reference input current REFP0 = VREF, REFN0 = AVSS ±10 nA
INTERNAL OSCILLATOR
Internal oscillator accuracy Normal mode –2% ±1% 2%
EXCITATION CURRENT SOURCES (IDACs)
Current settings 50, 100, 250, 500, 1000, 1500 µA
Compliance voltage All current settings AVDD – 0.9 V
Accuracy All current settings, each IDAC –6% ±1% 6%
Current match Between IDACs ±0.3%
Temperature drift Each IDAC 50 ppm/°C
Temperature drift matching Between IDACs 10 ppm/°C
TEMPERATURE SENSOR
Temperature sensor resolution Conversion resolution 14 Bits
Temperature resolution 0.03125 °C
Temperature sensor accuracy TA = 0°C to +75°C ±0.25 °C
TA = –40°C to +125°C ±0.5 °C
Temperature sensor accuracy vs analog supply voltage 0.0625 0.25 °C/V
LOW-SIDE POWER SWITCH
RON On-resistance 3.5 Ω
Current through switch 30 mA
DIGITAL INPUT/OUTPUT
VIH High-level input voltage 0.7 DVDD DVDD V
VIL Low-level input voltage DGND 0.3 DVDD V
VOH High-level output voltage IOH = 3 mA 0.8 DVDD V
VOL Low-level output voltage IOL = 3 mA 0.2 DVDD V
IH Input leakage, high VIH = 5.5 V –10 10 µA
IL Input leakage, low VIL = DGND –10 10 µA
POWER-SUPPLY
IAVDD Analog supply current(3) Power-down mode 0.1 3 µA
Duty-cycle mode, PGA disabled 65
Duty-cycle mode, gain = 1 to 16 95
Duty-cycle mode, gain = 32 115
Duty-cycle mode, gain = 64, 128 135
Normal mode, PGA disabled 240
Normal mode, gain = 1 to 16 340 490
Normal mode, gain = 32 425
Normal mode, gain = 64, 128 510
Turbo mode, PGA disabled 360
Turbo mode, gain = 1 to 16 540
Turbo mode, gain = 32 715
Turbo mode, gain = 64, 128 890
IDVDD Digital supply current(3) Power-down mode 0.3 5 µA
Duty-cycle mode 55
Normal mode 75 110
Turbo mode 95
PD Power dissipation(3) Duty-cycle mode, PGA disabled 0.4 mW
Normal mode, gain = 1 to 16 1.4
Turbo mode, gain = 1 to 16 2.1
(1) PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case.
See the Bypassing the PGA section for more information.
(2) Minimum and maximum values are ensured by design and characterization data.
(3) Internal voltage reference selected, internal oscillator enabled, both IDACs turned off.