SBAS894A April 2018 – October 2018 ADS112C04
The RDATA command loads the output shift register with the most recent conversion result. Reading conversion data must be performed as shown in Figure 57 by using two I2C communication frames. The first frame is an I2C write operation where the R/W bit at the end of the address byte is 0 to indicate a write. In this frame, the host sends the RDATA command to the ADS112C04. The second frame is an I2C read operation where the R/W bit at the end of the address byte is 1 to indicate a read. The ADS112C04 reports the latest ADC conversion data in this second I2C frame. If a conversion finishes in the middle of the RDATA command byte, the state of the DRDY pin at the end of the read operation signals whether the old or the new result is loaded. If the old result is loaded, DRDY stays low, indicating that the new result is not read out. The new conversion result loads when DRDY is high.