SBASB89 May   2025 ADS117L14 , ADS117L18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Clock Dividers
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 External Clock
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
        2. 7.3.8.2 Low-Latency Filter (Sinc)
          1. 7.3.8.2.1 Sinc4 Filter
          2. 7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter
          3. 7.3.8.2.3 Sinc3 Filter
          4. 7.3.8.2.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
        1. 7.4.1.1 RESET Pin
        2. 7.4.1.2 Reset by SPI Register
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2 Idle and Standby Modes
      3. 7.4.3 Power-Down
      4. 7.4.4 Speed Modes
      5. 7.4.5 Synchronization
        1. 7.4.5.1 Synchronized Control Mode
        2. 7.4.5.2 Start/Stop Control Mode
      6. 7.4.6 Conversion-Start Delay Time
      7. 7.4.7 Calibration
        1. 7.4.7.1 Offset Calibration Registers
        2. 7.4.7.2 Gain Calibration Registers
        3. 7.4.7.3 Calibration Procedure
      8. 7.4.8 Diagnostics
        1. 7.4.8.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.8.2 SPI CRC
        3. 7.4.8.3 Register Map CRC
        4. 7.4.8.4 ADC Error
        5. 7.4.8.5 SPI Address Range
        6. 7.4.8.6 SCLK Counter
        7. 7.4.8.7 Clock Counter
        8. 7.4.8.8 Frame-Sync CRC
        9. 7.4.8.9 Self Test
      9. 7.4.9 Frame-Sync Data Port
        1. 7.4.9.1  Data Packet
        2. 7.4.9.2  Data Format
        3. 7.4.9.3  STATUS_DP Header Byte
        4. 7.4.9.4  FSYNC Pin
        5. 7.4.9.5  DCLK Pin
        6. 7.4.9.6  DOUTx Pins
        7. 7.4.9.7  DINx Pins
        8. 7.4.9.8  Time Division Multiplexing
        9. 7.4.9.9  Daisy Chain
        10. 7.4.9.10 DOUTx Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 Commands
        1. 7.5.4.1 Write Register Command
        2. 7.5.4.2 Read Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Anti-alias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD1 and AVSS
      2. 9.3.2 AVDD2
      3. 9.3.3 IOVDD
      4. 9.3.4 CAPA and CAPD
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter

The sinc4 + sinc1 filter is the cascade of the sinc4 filter and a sinc1 filters. The fixed OSR of the sinc4 stage (OSR = 32) multiplied by the OSR of the sinc1 stage determines the ADC output data rate. The sinc4 + sinc1 filter mode has shorter latency time than the single-stage sinc4 filter. Table 7-4 summarizes the sinc4 + sinc1 filter characteristics.

Table 7-4 Sinc4 + Sinc1 Cascade Filter Characteristics
MODEfCLK
(MHz)		OSR
(A × B)(2)		DATA RATE
(kSPS)		–3dB FREQUENCY
(kHz)		LATENCY TIME
(µs)(1)
Max speed32.76864
(32 × 2)		25687.4910.9
High speed25.620068.3513.9
Mid speed12.810034.1827.9
Low speed3.2258.544111
Max speed32.768128
(32 × 4)		12852.4414.8
High speed25.610040.9719.0
Mid speed12.85020.4937.9
Low speed3.212.55.121152
Max speed32.768320
(32 × 10)		51.222.3626.5
High speed25.64017.4734.0
Mid speed12.8208.73567.9
Low speed3.252.184272
Max speed32.768640
(32 × 20)		25.611.2846.0
High speed25.6208.81458.9
Mid speed12.8104.407118
Low speed3.22.51.102471
Max speed32.7681280
(32 × 40)		12.85.65885.1
High speed25.6104.420109
Mid speed12.852.210218
Low speed3.21.250.552871
Max speed32.7683200
(32 × 100)		5.122.266202
High speed25.641.770259
Mid speed12.820.885517
Low speed3.20.50.2212068
Max speed32.7686400
(32 × 200)		2.561.133398
High speed25.620.885509
Mid speed12.810.4431018
Low speed3.20.250.1114075
Max speed32.76812800
(32 × 400)		1.280.566788
High speed25.610.4421008
Mid speed12.80.50.2212017
Low speed3.20.1250.0558069
Max speed32.76832000
(32 × 1000)		0.5120.2261960
High speed25.60.40.1772508
Mid speed12.80.20.0895018
Low speed3.20.050.02220070
(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.
(2) A = First stage OSR, B = Second stage OSR.

Figure 7-20 illustrates the frequency response of the sinc4 + sinc1 filter for three OSR values. The combined frequency response is the overlaid response of the sinc4 and sinc1 filters. For low OSR values, the response profile is dominated by the roll-off of the sinc4 filter. Nulls in the frequency response occur at n · fDATA, n = 1, 2, 3, and so on. At the null frequencies, the filter has zero gain.

ADS117L14 ADS117L18 Sinc4 + Sinc1 Frequency ResponseFigure 7-20 Sinc4 + Sinc1 Frequency Response