The PGA contains an integrated output-voltage monitor. If the level of the PGA output voltage exceeds
AVDD – 0.15 V or drops below AVSS + 0.15 V, a flag is set to indicate that the output has gone beyond the output range of the PGA. Each PGA output VOUTN and VOUTP can trigger an overvoltage or undervoltage flag, giving a total of four flags. The PGA output voltage rail monitors are enabled with the FL_REF_EN bit of excitation current register 1. The PGA output voltage rail monitor block diagram is shown in Figure 77. If the PGA is bypassed, then the rail monitor is still operational and is sensing the connection at the input of the ADC.
The PGA output voltage rail monitors are:
Figure 78 shows an example of a PGA output voltage rail monitor overrange event and the respective behavior of the flags. A fault is latched during a conversion cycle. The flags are updated (set or cleared) only at the end of a conversion cycle.