SBAS999A June   2019  – January 2021 ADS125H01

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage Range
      2. 9.3.2 Analog Inputs (AINP, AINN)
        1. 9.3.2.1 ESD Diodes
        2. 9.3.2.2 Input Switch
      3. 9.3.3 Programmable Gain Amplifier (PGA)
        1. 9.3.3.1 PGA Operating Range
        2. 9.3.3.2 PGA Monitors
      4. 9.3.4 Reference Voltage
        1. 9.3.4.1 Reference Monitor
      5. 9.3.5 ADC Modulator
      6. 9.3.6 Digital Filter
        1. 9.3.6.1 Sinc Filter Mode
          1. 9.3.6.1.1 Sinc Filter Frequency Response
        2. 9.3.6.2 FIR Filter
        3. 9.3.6.3 50-Hz and 60-Hz Normal-Mode Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Control
        1. 9.4.1.1 Continuous-Conversion Mode
        2. 9.4.1.2 Pulse-Conversion Mode
        3. 9.4.1.3 Conversion Latency
        4. 9.4.1.4 Start-Conversion Delay
      2. 9.4.2 Clock Mode
      3. 9.4.3 Reset
        1. 9.4.3.1 Power-On Reset
        2. 9.4.3.2 Reset by RESETPin
        3. 9.4.3.3 Reset by Command
      4. 9.4.4 Calibration
        1. 9.4.4.1 Offset and Full-Scale Calibration
          1. 9.4.4.1.1 Offset Calibration Registers
          2. 9.4.4.1.2 Full-Scale Calibration Registers
        2. 9.4.4.2 Offset Calibration Command (OFSCAL)
        3. 9.4.4.3 Full-Scale Calibration Command (GANCAL)
        4. 9.4.4.4 Calibration Command Procedure
        5. 9.4.4.5 User Calibration Procedure
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip-Select Pins (CS1 and CS2)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
      2. 9.5.2 Data Ready (DRDY)
        1. 9.5.2.1 DRDY in Continuous-Conversion Mode
        2. 9.5.2.2 DRDY in Pulse-Conversion Mode
        3. 9.5.2.3 Data Ready by Software Polling
      3. 9.5.3 Conversion Data
        1. 9.5.3.1 Status Byte (STATUS0)
        2. 9.5.3.2 Conversion Data Format
      4. 9.5.4 Cyclic Redundancy Check (CRC)
      5. 9.5.5 Commands
        1. 9.5.5.1  General Command Format
        2. 9.5.5.2  NOP Command
        3. 9.5.5.3  RESET Command
        4. 9.5.5.4  START Command
        5. 9.5.5.5  STOP Command
        6. 9.5.5.6  RDATA Command
        7. 9.5.5.7  OFSCAL Command
        8. 9.5.5.8  GANCAL Command
        9. 9.5.5.9  RREG Command
        10. 9.5.5.10 WREG Command
    6. 9.6 Register Map
      1. 9.6.1  Device Identification (ID) Register (address = 00h) [reset = 4xh]
      2. 9.6.2  Main Status (STATUS0) Register (address = 01h) [reset = 01h]
      3. 9.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
      4. 9.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
      5. 9.6.5  Reserved (RESERVED) Register (address = 04h) [reset = 00h]
      6. 9.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
      7. 9.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
      8. 9.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
      9. 9.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
      10. 9.6.10 Reserved (RESERVED) Register (address = 0Dh) [reset = FFh]
      11. 9.6.11 Reserved (RESERVED) Register (address = 0Eh) [reset = 00h]
      12. 9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
      13. 9.6.13 MODE4 (MODE4) Register (address = 10h) [reset = 50h]
      14. 9.6.14 PGA Alarm (STATUS1) Register (address = 11h) [reset = xxh]
      15. 9.6.15 Status 2 (STATUS2) Register (address = 12h) [reset = 0xh]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Example to Determine the PGA Linear Operating Range
      2. 10.1.2 Input Signal Rate of Change (dV/dt)
      3. 10.1.3 Unused Inputs and Outputs
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1 Overview

The ADS125H01 is a ±20-V signal input, 40-kSPS, 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC). The ADC provides a compact one-chip measurement solution for a wide range of input voltages, including typical current and voltage inputs of industrial programmable logic controllers (PLCs), such as ±10-V and 4-mA to 20-mA transmitters (using an external shunt resistor). The ADC provides the resolution necessary for direct interface to low-level sensors such as strain-gauge sensors and thermocouples.

The device features a programmable gain amplifier (PGA) with an attenuation range from 0.125 to 0.5 and a gain range from 1 to 128. The combination of attenuation and gain provide an overall input voltage range of ±20 V to ±20 mV (when VREF = 2.5 V). The PGA is low-noise and low-drift with high input impedance, and includes internal monitors for detection of overload conditions.

In summary, the ADC features:

  • 24-bit resolution
  • Low-noise, 1-GΩ input impedance PGA
  • Selectable attenuation and gain: overall full-scale range from ±20 mV to ±20 V
  • Internal or external clock operation
  • PGA and voltage reference monitors
  • SPI-compatible serial interface with cyclic redundancy check (CRC) error check

Analog inputs (AINP and AINN) connect to the PGA via an input switch. The switch selects between the input signal and an internal test voltage (VCM). Internal diodes protect the analog and reference inputs from ESD events.

The PGA is a high-impedance, differential-input and differential-output amplifier providing both gain and attenuation modes. In attenuation mode, the input voltage is reduced to the range of the ADC. In gain mode, the input voltage is amplified to the range of the ADC. The PGA output connects to the CAPP and CAPN pins. The ADC antialias filter is provided by the combination of the internal PGA output resistors and the external capacitor connected to these pins.

The PGA is monitored for signal overload conditions. Status bits in the STATUS1 register indicate possible PGA overload conditions.

The ΔΣ modulator measures the input voltage relative to the reference voltage to produce a 24-bit conversion result. The input range of the ADC is ±VREF / Gain, where gain is programmable from 0.125 to 128.

The reference voltage is either external (pins REFP, REFN) or the AVDD power supply. The reference input includes a monitor to detect low voltage conditions. The status is reflected in the conversion data STATUS byte.

The digital filter averages and decimates the modulator data to provide the output conversion result. For data rates ≤ 7.2 kSPS, the digital filter provides programmable sinc orders allowing optimization of conversion latency, conversion noise, and line-cycle rejection. The finite-impulse response (FIR) filter mode provides no-latency conversion data with simultaneous rejection of 50-Hz and 60-Hz interference at data rates of 20 SPS or less.

User-programmable offset- and gain-calibration registers correct the conversion data to provide the final conversion result.

The SPI-compatible serial interface is used to read the conversion data and for device configuration. SPI I/O communication is validated by CRC error checking. The serial interface consists of the following signals: CS1, CS2, SCLK, DIN, and DOUT/DRDY (see the Section 9.5.1.1 section for details). The dual-function DOUT/DRDY pin combines the functions of the serial data output and data-ready indication into one pin. DRDY is the data-ready output signal.

Clock operation is either by the internal oscillator or by an external clock source. The external clock is automatically detected by the ADC. The nominal clock frequency is 7.3728 MHz (10.24 MHz for fDATA = 40 kSPS).

Conversions are controlled by the START pin or by the START command. Conversions are programmable for either continuous or one-shot (pulse) mode of operation.

The ADC is reset at power-on, or manually reset by the RESET input or by the RESET command.

The HV_AVDD and HV_AVSS power supplies allow either bipolar or unipolar configuration (bipolar: ±5 V to ±18 V, unipolar: 10 V to 36 V). The 5-V analog supply (AVDD) powers the ADC. The digital I/Os are powered by DVDD (3-V to 5-V range). An internal 2-V subregulator powers the ADC digital core from the DVDD supply. An external bypass capacitor is required at the subregulator output (BYPASS pin).