SBAS661C February   2015  – May 2021 ADS1262 , ADS1263


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Offset Temperature Drift Measurement
    2. 8.2 Gain Temperature Drift Measurement
    3. 8.3 Common-Mode Rejection Ratio Measurement
    4. 8.4 Power-Supply Rejection Ratio Measurement
    5. 8.5 Crosstalk Measurement (ADS1263)
    6. 8.6 Reference-Voltage Temperature-Drift Measurement
    7. 8.7 Reference-Voltage Thermal-Hysteresis Measurement
    8. 8.8 Noise Performance
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multifunction Analog Inputs
      2. 9.3.2  Analog Input Description
        1. ESD Diode
        2. Input Multiplexer
      3. 9.3.3  Sensor Bias
      4. 9.3.4  Temperature Sensor
      5. 9.3.5  Power-Supply Monitor
      6. 9.3.6  PGA
      7. 9.3.7  PGA Voltage Overrange Monitors
        1. PGA Differential Output Monitor
        2. PGA Absolute Output-Voltage Monitor
      8. 9.3.8  ADC Reference Voltage
        1. Internal Reference
        2. External Reference
        3. Power-Supply Reference
        4. Low-Reference Monitor
      9. 9.3.9  ADC1 Modulator
      10. 9.3.10 Digital Filter
        1. Sinc Filter Mode
          1. Sinc Filter Frequency Response
        2. FIR Filter
        3. 50-Hz and 60-Hz Line Cycle Rejection
      11. 9.3.11 Sensor-Excitation Current Sources (IDAC1 and IDAC2)
      12. 9.3.12 Level-Shift Voltage
      13. 9.3.13 General-Purpose Input/Output (GPIO)
      14. 9.3.14 Test DAC (TDAC)
      15. 9.3.15 ADC2 (ADS1263)
        1. ADC2 Inputs
        2. ADC2 PGA
        3. ADC2 Reference
        4. ADC2 Modulator
        5. ADC2 Digital Filter
    4. 9.4 Device Functional Modes
      1. 9.4.1  Conversion Control
        1. Continuous Conversion Mode
        2. Pulse Conversion Mode
        3. ADC2 Conversion Control (ADS1263)
      2. 9.4.2  Conversion Latency
      3. 9.4.3  Programmable Time Delay
      4. 9.4.4  Serial Interface
        1. Chip Select (CS)
        2. Serial Clock (SCLK)
        3. Data Input (DIN)
        4. Data Output/Data Ready (DOUT/DRDY)
        5. Serial Interface Autoreset
      5. 9.4.5  Data Ready Pin (DRDY)
      6. 9.4.6  Conversion Data Software Polling
      7. 9.4.7  Read Conversion Data
        1. Read Data Direct (ADC1 Only)
        2. Read Data by Command
        3. Data-Byte Sequence
          1. Status Byte
          2. Data Byte Format
          3. Checksum Byte (CRC/CHK)
            1. Checksum Mode (CRC[1:0] = 01h)
          4. CRC Mode (CRC[1:0] = 10h)
      8. 9.4.8  ADC Clock Modes
        1. Internal Oscillator
        2. External Clock
        3. Crystal Oscillator
      9. 9.4.9  Calibration
        1. Offset and Full-Scale Calibration
          1. Offset Calibration Registers
          2. Full-Scale Calibration Registers
        2. ADC1 Offset Self-Calibration (SFOCAL1)
        3. ADC1 Offset System Calibration (SYOCAL1)
        4. ADC2 Offset Self-Calibration ADC2 (SFOCAL2)
        5. ADC2 Offset System Calibration ADC2 (SYOCAL2)
        6. ADC1 Full-Scale System Calibration (SYGCAL1)
        7. ADC2 Full-Scale System Calibration ADC2 (SYGCAL2)
        8. Calibration Command Procedure
        9. User Calibration Procedure
      10. 9.4.10 Reset
        1. Power-On Reset (POR)
        2. RESET/PWDN Pin
        3. Reset by Command
      11. 9.4.11 Power-Down Mode
      12. 9.4.12 Chop Mode
    5. 9.5 Programming
      1. 9.5.1 NOP Command
      2. 9.5.2 RESET Command
      3. 9.5.3 START1, STOP1, START2, STOP2 Commands
      4. 9.5.4 RDATA1, RDATA2 Commands
      5. 9.5.5 SYOCAL1, SYGCAL1, SFOCAL1, SYOCAL2, SYGCAL2, SFOCAL2 Commands
      6. 9.5.6 RREG Command
      7. 9.5.7 WREG Command
    6. 9.6 Register Maps
      1. 9.6.1  Device Identification Register (address = 00h) [reset = x]
      2. 9.6.2  Power Register (address = 01h) [reset = 11h]
      3. 9.6.3  Interface Register (address = 02h) [reset = 05h]
      4. 9.6.4  Mode0 Register (address = 03h) [reset = 00h]
      5. 9.6.5  Mode1 Register (address = 04h) [reset = 80h]
      6. 9.6.6  Mode2 Register (address = 05h) [reset = 04h]
      7. 9.6.7  Input Multiplexer Register (address = 06h) [reset = 01h]
      8. 9.6.8  Offset Calibration Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
      9. 9.6.9  Full-Scale Calibration Registers (address = 0Ah, 0Bh, 0Ch) [reset = 40h, 00h, 00h]
      10. 9.6.10 IDACMUX Register (address = 0Dh) [reset = BBh]
      11. 9.6.11 IDACMAG Register (address = 0Eh) [reset = 00h]
      12. 9.6.12 REFMUX Register (address = 0Fh) [reset = 00h]
      13. 9.6.13 TDACP Control Register (address = 10h) [reset = 00h]
      14. 9.6.14 TDACN Control Register (address = 11h) [reset = 00h]
      15. 9.6.15 GPIO Connection Register (address = 12h) [reset = 00h]
      16. 9.6.16 GPIO Direction Register (address = 13h) [reset = 00h]
      17. 9.6.17 GPIO Data Register (address = 14h) [reset = 00h]
      18. 9.6.18 ADC2 Configuration Register (address = 15h) [reset = 00h]
      19. 9.6.19 ADC2 Input Multiplexer Register (address = 16h) [reset = 01h]
      20. 9.6.20 ADC2 Offset Calibration Registers (address = 17h, 18h) [reset = 00h, 00h]
      21. 9.6.21 ADC2 Full-Scale Calibration Registers (address = 19h, 1Ah) [reset = 00h, 40h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Isolated (or Floated) Inputs
      2. 10.1.2 Single-Ended Measurements
      3. 10.1.3 Differential Measurements
      4. 10.1.4 Input Range
      5. 10.1.5 Input Filtering
        1. Aliasing
      6. 10.1.6 Input Overload
      7. 10.1.7 Unused Inputs and Outputs
      8. 10.1.8 Voltage Reference
      9. 10.1.9 Serial Interface Connections
    2. 10.2 Typical Application
      1. 10.2.1 3-Wire RTD Measurement with Lead-Wire Compensation
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
    3. 10.3 What To Do and What Not To Do
    4. 10.4 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


The ADS1262 and ADS1263 are precision 32-bit, delta-sigma (ΔΣ) ADCs with an integrated analog front end (AFE) to simplify connection to sensors. A 32-bit ADC (ADC1) provides output data rates from 2.5 SPS to 38400 SPS for flexibility in resolution and data rates over a wide range of applications. The ADC low noise and low drift architecture make these devices suitable for precise digitization of low-level transducers, such as load cell bridges and temperature sensors. The ADS1263 includes an auxiliary 24-bit delta-sigma ADC (ADC2).

The ADS1262 and the ADS1263 incorporate several functions that provide increased utility. The key integrated functions include:

  • Low-drift voltage reference
  • Dual, matched, sensor-excitation current sources (IDAC)
  • Input-level-shift voltage
  • Eight GPIOs
  • Dual-sensor, bias current sources
  • Low-noise, CMOS PGA with integrated signal fault detection
  • Internal test signal source (TDAC)
  • Temperature sensor
  • Internal oscillator
  • Three sets of buffered external reference inputs with low reference voltage alarm

As shown in the Section 9.2, these devices feature 11 analog inputs that are configurable as either ten single-ended inputs, five differential inputs, or any combination, to either ADC1 or ADC2. Many of the analog inputs are multifunction as programmed by the user. The analog inputs can be programmed to the following extended functions:

  • Three external reference inputs: pins AIN0, AIN1, AIN2, AIN3, AIN4 and AIN5
  • Two sensor excitation current source: all analog input pins
  • Level shift (VBIAS): AINCOM pin
  • Eight GPIO: pins AIN3, AIN4, AIN5, AIN6, AIN7, AIN8, AIN9, AINCOM
  • Sensor break current source: all analog input pins
  • Two test signal output: pins AIN6, AIN7

Following the input multiplexer (mux), ADC1 features a high-impedance, CMOS, programmable gain amplifier (PGA). The PGA provides very low voltage and current noise, enabling direct connection to low-level transducers, and in many cases, eliminating the need for an external amplifier. The PGA gain is programmable from 1 V/V to 32 V/V in binary steps. The PGA can be bypassed to allow the input range to extend below ground. The PGA has voltage overrange monitors to improve the integrity of the conversion result. The PGA overrange alarm is latched during the conversion phase and appended to the conversion data. The programmable sensor bias uses a test current to help detect a failed sensor or sensor connection.

An inherently stable delta-sigma modulator measures the ratio of the input voltage to the reference voltage to provide the ADC result. The ADC operates with the internal 2.5-V reference, or with up to three external reference inputs. The external reference inputs are continuously monitored for low (or missing) voltage. The reference alarm status is latched during the conversion phase and appended to the conversion data. The REFOUT pin is the buffered 2.5-V internal voltage reference output.

Dual excitation current sources (IDAC) provide bias to resistance sensors (such as 3-wire RTD). The ADC integrates several system monitors for readback, such as temperature sensor and supply monitor. The ADC features an internal test signal voltage (TDAC) that is used to verify the ADC operation across all gains. The TDAC has two outputs to provide test voltages for single-ended and differential input configurations. Eight GPIO ports are available on the analog input pins.

The digital filter provides two functional modes, sinc and FIR, allowing optimization of settling time and line-cycle rejection. The sinx/x (sinc) filter is programmable to sinc orders one through four to tradeoff filter settling time and 50-Hz and 60-Hz line-cycle rejection. The finite impulse response (FIR) filter mode provides single-cycle settled data with 50-Hz and 60-Hz line cycle rejection at data rates up to 20 SPS.

The ADS1263 includes an auxiliary 24-bit delta-sigma ADC (ADC2) featuring buffered PGA inputs, gains from 1 V/V to 128 V/V, and data rates up to 800 SPS. All analog inputs and reference inputs are available to ADC2. ADC2 can be used to provide redundant measurements or system measurements such as sensor temperature compensation and thermocouple cold junction compensation (CJC). The ADS1263 is pin and functionally compatible to the ADS1262.

The SPI™-compatible serial interface is used to read the conversion data and also to configure and control the ADC. The serial interface consists of four signals: CS, SCLK, DIN and DOUT/DRDY. The conversion data are provided with a CRC code for improved data integrity. The dual function DOUT/DRDY output indicates when conversion data are ready and also provides the data output. The serial interface can be implemented with as little as three connections by tying CS low.

The ADC has three clock options: internal oscillator, external crystal, and external clock. The ADC detects the clock mode automatically. The nominal clock frequency is 7.3728 MHz.

ADC conversions are started by a control pin or by commands. The ADC can be programmed to free-run mode or perform one-shot conversions. The DRDY and DOUT/DRDY pins are driven low when the conversion data are ready. The RESET/PWDN digital input resets the ADC when momentarily pulsed low, and when held low, enables the ADC power-down mode.

The ADC operates with bipolar (± 2.5 V) supplies, or with a single 5-V supply. For single-supply operation, use the internal level-shift voltage to level-shift isolated (floating) sensors. The digital power-supply range is 2.7 V to 5.25 V. The BYPASS pin is the subregulator output (2 V) that is used for internal digital supply.