SBAS661C February   2015  – May 2021 ADS1262 , ADS1263

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Serial Interface
    7. 7.7 Switching Characteristics: Serial Interface
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Offset Temperature Drift Measurement
    2. 8.2 Gain Temperature Drift Measurement
    3. 8.3 Common-Mode Rejection Ratio Measurement
    4. 8.4 Power-Supply Rejection Ratio Measurement
    5. 8.5 Crosstalk Measurement (ADS1263)
    6. 8.6 Reference-Voltage Temperature-Drift Measurement
    7. 8.7 Reference-Voltage Thermal-Hysteresis Measurement
    8. 8.8 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multifunction Analog Inputs
      2. 9.3.2  Analog Input Description
        1. 9.3.2.1 ESD Diode
        2. 9.3.2.2 Input Multiplexer
      3. 9.3.3  Sensor Bias
      4. 9.3.4  Temperature Sensor
      5. 9.3.5  Power-Supply Monitor
      6. 9.3.6  PGA
      7. 9.3.7  PGA Voltage Overrange Monitors
        1. 9.3.7.1 PGA Differential Output Monitor
        2. 9.3.7.2 PGA Absolute Output-Voltage Monitor
      8. 9.3.8  ADC Reference Voltage
        1. 9.3.8.1 Internal Reference
        2. 9.3.8.2 External Reference
        3. 9.3.8.3 Power-Supply Reference
        4. 9.3.8.4 Low-Reference Monitor
      9. 9.3.9  ADC1 Modulator
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Sinc Filter Mode
          1. 9.3.10.1.1 Sinc Filter Frequency Response
        2. 9.3.10.2 FIR Filter
        3. 9.3.10.3 50-Hz and 60-Hz Line Cycle Rejection
      11. 9.3.11 Sensor-Excitation Current Sources (IDAC1 and IDAC2)
      12. 9.3.12 Level-Shift Voltage
      13. 9.3.13 General-Purpose Input/Output (GPIO)
      14. 9.3.14 Test DAC (TDAC)
      15. 9.3.15 ADC2 (ADS1263)
        1. 9.3.15.1 ADC2 Inputs
        2. 9.3.15.2 ADC2 PGA
        3. 9.3.15.3 ADC2 Reference
        4. 9.3.15.4 ADC2 Modulator
        5. 9.3.15.5 ADC2 Digital Filter
    4. 9.4 Device Functional Modes
      1. 9.4.1  Conversion Control
        1. 9.4.1.1 Continuous Conversion Mode
        2. 9.4.1.2 Pulse Conversion Mode
        3. 9.4.1.3 ADC2 Conversion Control (ADS1263)
      2. 9.4.2  Conversion Latency
      3. 9.4.3  Programmable Time Delay
      4. 9.4.4  Serial Interface
        1. 9.4.4.1 Chip Select (CS)
        2. 9.4.4.2 Serial Clock (SCLK)
        3. 9.4.4.3 Data Input (DIN)
        4. 9.4.4.4 Data Output/Data Ready (DOUT/DRDY)
        5. 9.4.4.5 Serial Interface Autoreset
      5. 9.4.5  Data Ready Pin (DRDY)
      6. 9.4.6  Conversion Data Software Polling
      7. 9.4.7  Read Conversion Data
        1. 9.4.7.1 Read Data Direct (ADC1 Only)
        2. 9.4.7.2 Read Data by Command
        3. 9.4.7.3 Data-Byte Sequence
          1. 9.4.7.3.1 Status Byte
          2. 9.4.7.3.2 Data Byte Format
          3. 9.4.7.3.3 Checksum Byte (CRC/CHK)
            1. 9.4.7.3.3.1 Checksum Mode (CRC[1:0] = 01h)
          4. 9.4.7.3.4 CRC Mode (CRC[1:0] = 10h)
      8. 9.4.8  ADC Clock Modes
        1. 9.4.8.1 Internal Oscillator
        2. 9.4.8.2 External Clock
        3. 9.4.8.3 Crystal Oscillator
      9. 9.4.9  Calibration
        1. 9.4.9.1 Offset and Full-Scale Calibration
          1. 9.4.9.1.1 Offset Calibration Registers
          2. 9.4.9.1.2 Full-Scale Calibration Registers
        2. 9.4.9.2 ADC1 Offset Self-Calibration (SFOCAL1)
        3. 9.4.9.3 ADC1 Offset System Calibration (SYOCAL1)
        4. 9.4.9.4 ADC2 Offset Self-Calibration ADC2 (SFOCAL2)
        5. 9.4.9.5 ADC2 Offset System Calibration ADC2 (SYOCAL2)
        6. 9.4.9.6 ADC1 Full-Scale System Calibration (SYGCAL1)
        7. 9.4.9.7 ADC2 Full-Scale System Calibration ADC2 (SYGCAL2)
        8. 9.4.9.8 Calibration Command Procedure
        9. 9.4.9.9 User Calibration Procedure
      10. 9.4.10 Reset
        1. 9.4.10.1 Power-On Reset (POR)
        2. 9.4.10.2 RESET/PWDN Pin
        3. 9.4.10.3 Reset by Command
      11. 9.4.11 Power-Down Mode
      12. 9.4.12 Chop Mode
    5. 9.5 Programming
      1. 9.5.1 NOP Command
      2. 9.5.2 RESET Command
      3. 9.5.3 START1, STOP1, START2, STOP2 Commands
      4. 9.5.4 RDATA1, RDATA2 Commands
      5. 9.5.5 SYOCAL1, SYGCAL1, SFOCAL1, SYOCAL2, SYGCAL2, SFOCAL2 Commands
      6. 9.5.6 RREG Command
      7. 9.5.7 WREG Command
    6. 9.6 Register Maps
      1. 9.6.1  Device Identification Register (address = 00h) [reset = x]
      2. 9.6.2  Power Register (address = 01h) [reset = 11h]
      3. 9.6.3  Interface Register (address = 02h) [reset = 05h]
      4. 9.6.4  Mode0 Register (address = 03h) [reset = 00h]
      5. 9.6.5  Mode1 Register (address = 04h) [reset = 80h]
      6. 9.6.6  Mode2 Register (address = 05h) [reset = 04h]
      7. 9.6.7  Input Multiplexer Register (address = 06h) [reset = 01h]
      8. 9.6.8  Offset Calibration Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
      9. 9.6.9  Full-Scale Calibration Registers (address = 0Ah, 0Bh, 0Ch) [reset = 40h, 00h, 00h]
      10. 9.6.10 IDACMUX Register (address = 0Dh) [reset = BBh]
      11. 9.6.11 IDACMAG Register (address = 0Eh) [reset = 00h]
      12. 9.6.12 REFMUX Register (address = 0Fh) [reset = 00h]
      13. 9.6.13 TDACP Control Register (address = 10h) [reset = 00h]
      14. 9.6.14 TDACN Control Register (address = 11h) [reset = 00h]
      15. 9.6.15 GPIO Connection Register (address = 12h) [reset = 00h]
      16. 9.6.16 GPIO Direction Register (address = 13h) [reset = 00h]
      17. 9.6.17 GPIO Data Register (address = 14h) [reset = 00h]
      18. 9.6.18 ADC2 Configuration Register (address = 15h) [reset = 00h]
      19. 9.6.19 ADC2 Input Multiplexer Register (address = 16h) [reset = 01h]
      20. 9.6.20 ADC2 Offset Calibration Registers (address = 17h, 18h) [reset = 00h, 00h]
      21. 9.6.21 ADC2 Full-Scale Calibration Registers (address = 19h, 1Ah) [reset = 00h, 40h]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Isolated (or Floated) Inputs
      2. 10.1.2 Single-Ended Measurements
      3. 10.1.3 Differential Measurements
      4. 10.1.4 Input Range
      5. 10.1.5 Input Filtering
        1. 10.1.5.1 Aliasing
      6. 10.1.6 Input Overload
      7. 10.1.7 Unused Inputs and Outputs
      8. 10.1.8 Voltage Reference
      9. 10.1.9 Serial Interface Connections
    2. 10.2 Typical Application
      1. 10.2.1 3-Wire RTD Measurement with Lead-Wire Compensation
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
    3. 10.3 What To Do and What Not To Do
    4. 10.4 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary

Package Options

Mechanical Data (Package|Pins)
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Orderable Information

9.3.15.5 ADC2 Digital Filter

The ADC2 digital filter receives the modulator output and produces a 24-bit digital output. The digital filter low-pass filters and down-samples the modulator data to yield the final data rate. The ADC2 digital filter is a cascade of two stages. The first stage is a sinc3 filter that decimates by 64, 128, or 512, to derive data rates of 800 SPS, 400 SPS, or 100 SPS, respectively. The second stage receives the output of the first stage at 100 SPS. The second stage is a sinc1 filter with decimation equal to ten that derives the data rate of 10 SPS, as illustrated in Figure 9-31. The ADC bypasses the second stage for data rates of 800 SPS, 400 SPS, and 100 SPS. Table 9-10 shows the sinc filter data rates and decimation ratios (A and B) that correspond to each filter stage. The overall filter decimation ratio is the product of A and B decimation ratios. The data rate is programmed by the DR2[1:0] bits of register ADC2CFG.

GUID-E8B9A94E-8322-414A-9DAD-CC57CB621CAB-low.gifFigure 9-31 ADC2 Digital Filter Block Diagram
Table 9-10 ADC2 Data Rates and Filter Decimation Ratios
DATA RATE (SPS)(1)DR2[1:0] BITS OF REGISTER ADC2CFG1st STAGE DECIMATION RATIO A2nd STAGE DECIMATION RATIO B
10 ( default)0051210
10001512-
40010128-
8001164-
(1) fCLK = 7.3728 MHz. The data rate scales with fCLK.

The low pass nature of the ADC2 sinc filter establishes the overall frequency response. The frequency response is given by Equation 17:

Equation 17. GUID-8B39A8D7-FC88-4744-839A-4E82C9F35828-low.gif

where

  • f = Input frequency
  • fCLK = ADC clock (7.3728 MHz)
  • A = First stage decimation ratio
  • B = Second stage decimation ratio

Figures Figure 9-32 through Figure 9-36 show the frequency response of different ADC2 data rates. Nulls are located in the frequency response at the data rate and at data rate multiples. Figure 9-32 (data rate = 10 SPS) has frequency response nulls at 50 Hz and 60 Hz and their multiples. Therefore, the rate of 10 SPS provides rejection of power line cycle frequencies. Figure 9-33 shows filter response detail of frequencies centered around 50 Hz and 60 Hz.

GUID-5E5E1401-3E06-4F8D-84A4-8F02D0D9C2F0-low.gifFigure 9-32 ADC2 10 SPS Frequency Response
GUID-44D48D51-4940-4061-A126-F320084A9617-low.gifFigure 9-34 ADC2 100 SPS Frequency Response
GUID-74A1749F-1CF1-4585-B033-1A717BD52790-low.gifFigure 9-36 ADC2 800 SPS Frequency Response
GUID-91DA0861-9420-400F-9860-F257DD48BAC4-low.gifFigure 9-33 ADC2 10 SPS Frequency Response 50-Hz and 60-Hz Detail
GUID-5D64D0D7-CB22-4CA1-B66C-F094EDAF1200-low.gifFigure 9-35 ADC2 400 SPS Frequency Response

Table 9-11 summarizes the ADC2 digital filter –3-dB bandwidth and 50-Hz and 60-Hz line-cycle rejection based on 2% and 6% ratio tolerance of power-line frequency to ADC clock frequency. The sample rate of 10 SPS has frequency response nulls at 50 Hz and 60 Hz; therefore, this data rate provides the best possible rejection of power-line interference.

Table 9-11 ADC2 –3-dB Bandwidth, 50-Hz and 60-Hz Line Cycle Rejection
DATA RATE (SPS)-3-dB BANDWIDTH (Hz)DIGITAL FILTER RESPONSE (dB)
50-Hz REJECTION ±2%60-Hz REJECTION ±2%50-Hz REJECTION ±6%60-Hz REJECTION ±6%
104.4–41–47–32–36
10026–12–17–10–16
400104–0.5–0.9–0.5–0.9
800208–0.2–0.2–0.1–0.2

The ADC digital filter provides attenuation of frequencies greater than ½ of the data rate (Nyquist frequency) to minimize out-of-band frequencies folding back to the bandwidth of interest. As with all digital filters, response images appear at frequency multiples of the filter input frequency (fMOD2 = fCLK / 144 = 51.2 kHz). Figure 9-37 shows the frequency response to 175 kHz for DR = 800 SPS. The response near dc is the desired signal bandwidth. Note how the filter response repeats at multiplies of 51.2 kHz. The filter response repeats at frequencies shown in Equation 18:

Equation 18. Aliased frequency bands = N · fMOD2 ± fDR2

where

  • N = 1, 2, 3...
  • fDR2 = ADC2 data-rate frequency

The digital filter attenuates signal or noise up to the frequency where the response repeats. However, any signal or noise present within the frequency bands where the response repeats aliases into the passband, unless attenuated by an analog filter. Often, using a simple RC analog filter is sufficient to reject these frequencies.

GUID-A020F61B-9A23-4A52-ABCB-65402C479E2F-low.gifFigure 9-37 ADC2 Frequency Response to 175 kHz