The device uses a chopper-stabilized PGA and modulator in order to provide very low input voltage offset drift (VOS/dT). However, because of nonidealities arising from chopper stabilization, a small amount of offset voltage drift sometimes remains. ADC1 incorporates a global chop option to reduce the offset voltage and offset voltage drift to very low levels. When Chop is enabled, the ADC performs two internal conversions to cancel the input offset voltage. The first conversion is taken with normal input polarity. The ADC reverses the internal input polarity for the second conversion. The difference of the two conversions is computed to yield the final corrected result with the offset voltage removed. See Figure 9-55. The ADC internal offset voltage is modeled as VOFS.
The following is the internal Chop mode sequence.
Internal Conversion 1: VAINP - VAINN - VOFS => First conversion withheld
Internal Conversion 2: VAINN - VAINP - VOFS => Output result 1 = (Conversion 1 - Conversion 2) /2 = VAINP - VAINN
Internal Conversion 3: VAINP - VAINN - VOFS => Output result 2 = (Conversion 3 - Conversion 2) /2 = VAINP - VAINN
Internal Conversion 4: VAINN - VAINP - VOFS => Output result 3 = (Conversion 3 - Conversion 4) /2 = VAINP - VAINN
The internal chop sequence repeats for all successive conversions.
As a result of the delay required by the digital filter to settle after reversing the inputs, the chop-mode data rate is less than the nominal data rate, depending on the digital filter order and programmed settling delay. Nevertheless, if the data rate currently in use has 50-Hz and 60-Hz frequency response nulls, the null frequencies remain unchanged. Chop mode also reduces the ADC noise by a factor of 1.4 because of the averaging of two conversions. In some cases, it is necessary to increase the time delay parameter, DELAY[3:0], to allow for settling of external components.