After the power supplies are turned on, the ADC remains in reset until VDVDD, the internal LDO output (BYPASS pin voltage), and the combined (VAVDD – VAVSS) power supply voltage have exceeded their respective POR voltage thresholds. Figure 9-52 shows the POR sequence. When the power supplies have crossed the voltage thresholds, the ADC is operational 65536 fCLK cycles later (9 ms, typical). Note the 1-µF capacitor connected to the BYPASS pin requires charging at power-on, and as a result, can delay when the ADC is operational. Wait at least 9 ms after the power supplies have fully stabilized before beginning ADC communication.
|VDIGITAL_POR||Digital power supply POR threshold||VDVDD and VBYPASS||1||V|
|VANALOG_POR||Analog power supply POR threshold||VAVDD – VAVSS||3.5||V|
|td(POROP)||Propagation delay from last POR supply threshold to ADC operational||65536||tCLK(1)|