In addition to hardware polling using DRDY, new conversion data are also detected by software polling. In software polling, read either ADC1 or ADC2 conversion data and poll the STATUS byte ADC1 or ADC2 data-ready bits. The data ready bits are set if the corresponding ADC1 or ADC2 conversion data are new since the last ADC1 or ADC2 data read; otherwise, the bits are cleared. If the bits are cleared, the corresponding conversion data are the previous data. To avoid missing data when using software polling, poll the status bits at a rate faster than the corresponding ADC1 or ADC2 conversion rate. The ADC2 status bit is valid only when the data are read by command (RDATA1 or RDATA2).