The DRDY pin is an output that transitions low to indicate when ADC1 conversion data are ready for retrieval. Figure 9-42 depicts the DRDY operation. Initially, DRDY is high at power-on. When converting, the state of DRDY depends on the conversion mode (continuous or pulse) and whether the conversion data are retrieved or not. In Continuous conversion mode, after DRDY goes low, DRDY is driven high on the first SCLK falling edge. If data are not read, DRDY remains low and then pulses high 16 fCLK cycles before the next DRDY falling edge. The data must be retrieved before the next DRDY falling edge otherwise the data are overwritten by new data and previous data are lost. In Pulse mode, DRDY is driven high when a conversion is started and goes low when the conversion data are ready. DRDY remains low until the next conversion is started.
The DOUT/DRDY output operates similarly to DRDY. DOUT/DRDY transitions low when ADC1 conversion data are ready. If data are not retrieved, the DOUT/DRDY pin stays low and is pulsed high for 16 fCLK cycles at the next data ready. Note that CS must be low to enable the DOUT/DRDY pin.
|tc(DR)||DRDY↓ to DRDY↓ conversion time: DRDY period||After first conversion||1||1/data rate|
|tw(DRL)||DRDY↓to DRDY↑: delay time||With data retrieval, Continuous conversion mode||DRDY drives high on first falling SCLK edge|
|tw(DRH)||DRDY pulse high: pulse duration||No data retrieval, Continuous conversion mode,||16||tCLK(1)|