The ADC conversion process requires a clock for operation. These devices have three clock operating modes:
The nominal clock frequency is 7.3728 MHz. The output data rate and the corresponding 50-Hz and 60-Hz filter response nulls scale with clock frequency. Good line-cycle rejection requires an accurate clock frequency that is best provided by a crystal oscillator.
As depicted in Figure 9-49, the ADC contains an integrated clock generator and automatic detection circuit. If no external clock is detected, the ADC automatically selects the internal oscillator. If an external clock is detected, the ADC automatically selects the external clock. The clock mode can be verified by reading the EXTCLK bit, bit 5 of the status byte (0 = internal clock).
Figure 9-50 illustrates the configuration for the three clock modes.