After power up, take the CS input high to reset the ADC serial interface. CS high resets the serial interface in the event an unintentional SCLK glitch has occurred during power-on initialization. If CS is tied low, glitches at SCLK power on can interrupt synchronization to the serial interface and must be avoided. In this case, reset the ADC using the RESET/PWDN input. The SCLK input is edge sensitive, and therefore must be free of noise, glitches, and overshoot. Use a terminating resistor located at the SCLK buffer to smooth the edges and reduce overshoot.
Most microcontroller SPI peripherals can operate with the ADC. The interface operates in SPI mode 1, where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are updated or changed on SCLK rising edges; data are latched or read by the host and the ADC on SCLK falling edges. Details of the SPI communication protocol employed by the device is found in the Section 7.6 table. Place a 47-Ω resistor in series with all digital input and output pins (CS, SCLK, DIN, DOUT/DRDY, and DRDY). The resistors match the characteristic impedance of the PCB trace by source termination, helping reduce overshoot and ringing.