The ADC2 digital filter receives the modulator output and produces a 24-bit digital output. The digital filter low-pass filters and down-samples the modulator data to yield the final data rate. The ADC2 digital filter is a cascade of two stages. The first stage is a sinc3 filter that decimates by 64, 128, or 512, to derive data rates of 800 SPS, 400 SPS, or 100 SPS, respectively. The second stage receives the output of the first stage at 100 SPS. The second stage is a sinc1 filter with decimation equal to ten that derives the data rate of 10 SPS, as illustrated in Figure 9-31. The ADC bypasses the second stage for data rates of 800 SPS, 400 SPS, and 100 SPS. Table 9-10 shows the sinc filter data rates and decimation ratios (A and B) that correspond to each filter stage. The overall filter decimation ratio is the product of A and B decimation ratios. The data rate is programmed by the DR2[1:0] bits of register ADC2CFG.
|DATA RATE (SPS)(1)||DR2[1:0] BITS OF REGISTER ADC2CFG||1st STAGE DECIMATION RATIO A||2nd STAGE DECIMATION RATIO B|
|10 ( default)||00||512||10|
The low pass nature of the ADC2 sinc filter establishes the overall frequency response. The frequency response is given by Equation 17:
Figures Figure 9-32 through Figure 9-36 show the frequency response of different ADC2 data rates. Nulls are located in the frequency response at the data rate and at data rate multiples. Figure 9-32 (data rate = 10 SPS) has frequency response nulls at 50 Hz and 60 Hz and their multiples. Therefore, the rate of 10 SPS provides rejection of power line cycle frequencies. Figure 9-33 shows filter response detail of frequencies centered around 50 Hz and 60 Hz.
Table 9-11 summarizes the ADC2 digital filter –3-dB bandwidth and 50-Hz and 60-Hz line-cycle rejection based on 2% and 6% ratio tolerance of power-line frequency to ADC clock frequency. The sample rate of 10 SPS has frequency response nulls at 50 Hz and 60 Hz; therefore, this data rate provides the best possible rejection of power-line interference.
|DATA RATE (SPS)||-3-dB BANDWIDTH (Hz)||DIGITAL FILTER RESPONSE (dB)|
|50-Hz REJECTION ±2%||60-Hz REJECTION ±2%||50-Hz REJECTION ±6%||60-Hz REJECTION ±6%|
The ADC digital filter provides attenuation of frequencies greater than ½ of the data rate (Nyquist frequency) to minimize out-of-band frequencies folding back to the bandwidth of interest. As with all digital filters, response images appear at frequency multiples of the filter input frequency (fMOD2 = fCLK / 144 = 51.2 kHz). Figure 9-37 shows the frequency response to 175 kHz for DR = 800 SPS. The response near dc is the desired signal bandwidth. Note how the filter response repeats at multiplies of 51.2 kHz. The filter response repeats at frequencies shown in Equation 18:
The digital filter attenuates signal or noise up to the frequency where the response repeats. However, any signal or noise present within the frequency bands where the response repeats aliases into the passband, unless attenuated by an analog filter. Often, using a simple RC analog filter is sufficient to reject these frequencies.