SBAS661C February 2015 – May 2021 ADS1262 , ADS1263
Figure 10-16 is a general procedure that shows a typical ADS1262 configuration and measurement sequence.
Figure 10-17 shows a general procedure to read concurrent ADC1 and ADC2 data of the ADS1263. The conversion time of ADC1 can be faster or slower than ADC2. If the conversion time of ADC1 is less than or equal to that of ADC2, and if the ADC2 status bit is equal to 1, then when ADC1 data are ready, ADC2 data are also ready. The ADC2 data can then be read by the RDATA2 command. Similarly, if the conversion time of ADC2 is less than that of ADC1, and if the ADC1 status bit is equal to 1, then when ADC2 data are ready. ADC1 data are also ready, The ADC1 data can then be read by the RDATA1 command. It is important to note an exception to the conversion time related to the data rate: the time of the first conversion is not always the same as (1 / data rate) because of digital filter latency. Therefore, it is possible that although the data rate of ADC1 can be faster than ADC2, the time required for the first conversion of ADC1 can be greater than ADC2 depending on the digital filter setting and chop mode. When checking the ADC2 status by reading ADC1 data, use the RDATA1 command.