The ADC1 PGA is a low-noise, programmable gain, CMOS differential-input, differential-output amplifier. The PGA extends the ADC dynamic range of sensors with low input-signal levels. The PGA provides gains of 1, 2, 4, 8 ,16, and 32. Bypass the PGA to extend the analog input range to below ground (if the AVSS pin is grounded).
Figure 9-6 shows the PGA block diagram. The PGA consists of two chopper-stabilized amplifiers (A1 and A2), and a resistor network that is programmed to set the PGA gain. The PGA input is equipped with a high-frequency, electromagnetic-interference (EMI) input filter consisting of two 350-Ω input resistors, and several filter capacitors, as shown in the figure. Bypass the PGA to directly connect the inputs to the ADC. The PGA output is monitored by an overrange voltage monitor. The voltage monitor triggers an alarm when the absolute or differential PGA output voltage exceeds the linear range of operation. Pins CAPP and CAPN are the PGA positive and negative outputs, respectively. Connect a 4.7-nF (C0G) capacitor as shown in the figure. The capacitor provides an analog antialias filter, as well as the deglitch filter for the modulator sample pulses. Place the capacitor close to the pins using short, direct traces. Avoid running clock traces or other digital traces close to the pins.
The ADC1 full-scale voltage range is determined by the reference voltage and the PGA gain. Table 9-2 shows the full-scale voltage range verses gain for reference voltage = 2.5 V. The full-scale voltage range scales with the reference voltage and is increased or decreased by changing the reference voltage.
|GAIN[2:0] BITS OF REGISTER MODE2||GAIN (V/V)||FULL SCALE RANGE (V)(1)|
As with many amplifiers, the PGA has an absolute input voltage range requirement that cannot be exceeded. The maximum and minimum absolute input voltages are limited by the voltage swing capability of the PGA output. The specified minimum and maximum absolute input voltages (VINP and VINN) depend on the PGA gain, the input differential voltage (VIN), and the tolerance of the analog power-supply voltages (VAVDD and VAVSS). The absolute positive and negative input voltages must be within the specified range, as shown in Equation 12:
The relationship between the PGA input to the PGA output is shown graphically in Figure 9-7. The PGA output voltages (VOUTP, VOUTN) depend on the PGA gain and the input voltage magnitudes. For linear operation, the PGA output voltages must not exceed VAVDD – 0.3 or VAVSS + 0.3. Note the diagram depicts a positive differential input voltage that results in a positive differential output voltage.
If the PGA is bypassed, the ADC absolute input voltage range extends beyond the VAVDD and VAVSS power supplies allowing input voltages at or below ground. The absolute input voltage range when the PGA is bypassed is shown in Equation 13: