Figure 100 illustrates a multiple device configuration where all devices are configured in synchronous slave mode. Figure 100 illustrates a master clock at the CLKIN pin, but a free-running SCLK can also be used as the conversion clock in this mode. SCLK must be free-running if the modulator clock is derived from the serial clock (CLKSRC = 1). See the Synchronous Slave Mode section for more information about clocking the device using SCLK. The DONE pin of each device connects to the CS pin of the subsequent device for communication. The DOUT pin of a device whose contents are already shifted out assumes a high-impedance state, allowing the DOUT pins of all devices to be tied together. To send commands to specific devices, send the respective command to the device when that device is selected for communication. In this configuration, conversions must be synchronized by the master. Synchronization is accomplished by tying the chip select or frame sync output of the host to the DRDY input of each device. The master must have a synchronous clock and must be able to send clocks at exactly the proper timing to maintain synchronization. See the Synchronous Slave Mode section for more information about conversion synchronization using slave mode. Figure 101 illustrates an example interface timing diagram for this configuration.
NOTE:(1) denotes device 1, (2) denotes device 2, and (N) denotes device N.