Cyclic redundancy check (CRC) is a method for detecting errors in data communication between the device and the master. The CRC uses a polynomial division with binary data and the remainder word becomes a check to verify that the communication is correct. The ADS131A0x implements a standard CRC16-CCITT algorithm using a polynomial of 11021h and an initial remainder of FFFFh.
The CRC word is the last device word in the DIN and DOUT data frame. The CRC device word is optional and is enabled by the CRC_EN control bit in the D_SYS_CFG register. When enabled, a 16-bit CRC data check word is present in the 16 most significant bits of the last device word in the data frame on both DIN and DOUT. Use the CRC to provide detection of single and multiple bit errors during data transmission.
The CRC on all DIN commands is verified by the device prior to command execution except for the WREGS command; see the WREGS: Write Multiple Registers section. The WREGS command does not check the CRC prior to writing registers but does indicate if an error occurred. If the CRC on DIN is incorrect, F_CHECK in the STAT_1 register is set to 1 and the input command does not execute (for all commands except WREGS). Fill the unused device words on DIN with zeroes, placing the CRC word in the last device word.
The number of input CRC errors is counted and stored in the error count register. The register counts errors up to 255 before rolling over to 0. The counter is cleared by reading the error count register.