SBASAP8A december   2022  – august 2023 ADS131B23

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Offset Drift Measurement
    2. 7.2 Gain Drift Measurement
    3. 7.3 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Naming Conventions
      2. 8.3.2 Precision Voltage References (REFA, REFB)
      3. 8.3.3 Clocking (MCLK, OSCM, OSCD)
      4. 8.3.4 ADC1y
        1. 8.3.4.1 ADC1y Input Multiplexer
        2. 8.3.4.2 ADC1y Programmable Gain Amplifier (PGA)
        3. 8.3.4.3 ADC1y ΔΣ Modulator
        4. 8.3.4.4 ADC1y Digital Filter
        5. 8.3.4.5 ADC1y Offset and Gain Calibration
        6. 8.3.4.6 ADC1y Conversion Data
      5. 8.3.5 ADC2y
        1. 8.3.5.1 ADC2y Input Multiplexer
        2. 8.3.5.2 ADC2y Programmable Gain Amplifier (PGA)
        3. 8.3.5.3 ADC2y ΔΣ Modulator
        4. 8.3.5.4 ADC2y Digital Filter
        5. 8.3.5.5 ADC2y Offset and Gain Calibration
        6. 8.3.5.6 ADC2y Sequencer
        7. 8.3.5.7 VCMy Buffers
        8. 8.3.5.8 ADC2y Measurement Configurations
        9. 8.3.5.9 ADC2y Conversion Data
      6. 8.3.6 General-Purpose Digital Inputs and Outputs (GPIO0 to GPIO4)
        1. 8.3.6.1 GPIOx PWM Output Configuration
        2. 8.3.6.2 GPIOx PWM Input Readback
      7. 8.3.7 General-Purpose Digital Inputs and Outputs (GPIO0A, GPIO1A, GPIO0B, GPIO1B)
      8. 8.3.8 Monitors and Diagnostics
        1. 8.3.8.1  Supply Monitors
        2. 8.3.8.2  Clock Monitors
        3. 8.3.8.3  Digital Monitors
          1. 8.3.8.3.1 Register Map CRC
          2. 8.3.8.3.2 Memory Map CRC
          3. 8.3.8.3.3 GPIO Readback
        4. 8.3.8.4  Communication Monitors
        5. 8.3.8.5  Fault Flags and Fault Masking
        6. 8.3.8.6  FAULT Pin
        7. 8.3.8.7  Diagnostics and Diagnostic Procedure
        8. 8.3.8.8  Indicators
        9. 8.3.8.9  Conversion and Sequence Counters
        10. 8.3.8.10 Supply Voltage Readback
        11. 8.3.8.11 Temperature Sensor (TSA)
        12. 8.3.8.12 Test DACs (TDACA, TDACB)
        13. 8.3.8.13 Open-Wire Detection
        14. 8.3.8.14 Missing Host Detection and MHD Pin
        15. 8.3.8.15 Overcurrent Comparators (OCCA, OCCB)
          1. 8.3.8.15.1 OCCA and OCCB Pins
          2. 8.3.8.15.2 Overcurrent Indication Response Time
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset (POR)
        2. 8.4.1.2 RESETn Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Active Mode
        2. 8.4.2.2 Standby Mode
        3. 8.4.2.3 Power-Down Mode
      3. 8.4.3 ADC Conversion Modes
        1. 8.4.3.1 ADC1y Conversion Modes
          1. 8.4.3.1.1 Continuous-Conversion Mode
          2. 8.4.3.1.2 Single-Shot Conversion Mode
          3. 8.4.3.1.3 Global-Chop Mode
            1. 8.4.3.1.3.1 Overcurrent Indication Response Time in Global-Chop Mode
        2. 8.4.3.2 ADC2y Sequencer Operation and Sequence Modes
          1. 8.4.3.2.1 Continuous Sequence Mode
          2. 8.4.3.2.2 Single-Shot Sequence Mode
          3. 8.4.3.2.3 Synchronized Single-Shot Sequence Mode Based on ADC1y Conversion Starts
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Serial Interface Signals
          1. 8.5.1.1.1 Chip Select (CSn)
          2. 8.5.1.1.2 Serial Data Clock (SCLK)
          3. 8.5.1.1.3 Serial Data Input (SDI)
          4. 8.5.1.1.4 Serial Data Output (SDO)
          5. 8.5.1.1.5 Data Ready (DRDYn)
        2. 8.5.1.2 Serial Interface Communication Structure
          1. 8.5.1.2.1 SPI Communication Frames
          2. 8.5.1.2.2 SPI Communication Words
          3. 8.5.1.2.3 STATUS Word
          4. 8.5.1.2.4 Communication Cyclic Redundancy Check (CRC)
          5. 8.5.1.2.5 Commands
            1. 8.5.1.2.5.1 NULL (0000 0000 0000 0000b)
            2. 8.5.1.2.5.2 RESET (0000 0000 0001 0001b)
            3. 8.5.1.2.5.3 LOCK (0000 0101 0101 0101b)
            4. 8.5.1.2.5.4 UNLOCK (0000 0110 0101 0101b)
            5. 8.5.1.2.5.5 WREG (011a aaaa aaa0 0nnnb)
            6. 8.5.1.2.5.6 RREG (101a aaaa aaan nnnnb)
          6. 8.5.1.2.6 SCLK Counter
          7. 8.5.1.2.7 SPI Timeout
          8. 8.5.1.2.8 Reading ADC1A, ADC1B, and ADC2A Conversion Data
          9. 8.5.1.2.9 DRDYn Pin Behavior
    6. 8.6 Register Map
      1. 8.6.1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Minimum Interface Connections
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current-Shunt Measurement
        2. 9.2.2.2 Battery-Pack Voltage Measurement
        3. 9.2.2.3 Shunt Temperature Measurement
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Options
        1. 9.3.1.1 Single Unregulated External 4-V to 16-V Supply (3.3-V Digital I/O Levels)
        2. 9.3.1.2 Single Regulated External 3.3-V Supply (3.3-V Digital IO Levels)
        3. 9.3.1.3 Single Regulated External 5-V Supply (5-V Digital I/O Levels)
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1 Registers

Table 8-25 lists the memory-mapped registers for the Registers registers. All register offset addresses not listed in Table 8-25 should be considered as reserved locations and the register contents should not be modified.

Table 8-25 Register Map
AddressAcronymResetBit 15Bit 14Bit 13Bit 12Bit 11Bit 10Bit 9Bit 8
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
SECTION 0
00hIDXREV[7:0]
ADC_COUNT[2:0]DEVICE_ID[4:0]
01hSTATUS_MSB7FC8hRESETnSUPPLY_FAULTnCLOCK_FAULTnDIGITAL_FAULTnOCC_FAULTnSPI_CRC_FAULTnSPI_TIMEOUTnSCLK_COUNT_FAULTn
REG_ACCESS_FAULTnCOMMAND_RESPONSE[3:0]LOCKCLOCKMODE
02hSTATUS_LSB0000hSEQ2A_COUNT[1:0]RESERVEDCONV1A_COUNT[1:0]CONV1B_COUNT[1:0]
RESERVEDSEQ2A_ACTIVERESERVED
03hSUPPLY_STATUSFFFFhAVDD_OVnAVDD_UVnIOVDD_OVnIOVDD_UVnDVDD_OVnDVDD_UVnAVDD_OSCnIOVDD_OSCn
DVDD_OSCnAVDD_OTWnIOVDD_OTWnAVDD_CLnIOVDD_CLnAGNDA_DISCnAGNDB_DISCnDGND_DISCn
04hCLOCK_STATUSFC07hRESERVED
RESERVEDMCLK_FAULTnOSCD_WDnMCLK_WDn
05hDIGITAL_STATUSEC00hREG_MAP1_CRC_FAULTnREG_MAP2_CRC_FAULTnREG_MAP3_CRC_FAULTnRESERVEDMEM_MAP_CRC_FAULTnOTP_BANKRESERVED
RESERVED
06hOCC_STATUS000FhRESERVED
RESERVEDOCCA_HTnOCCA_LTnOCCB_HTnOCCB_LTn
07hGPI_DATA0000hRESERVEDGPI4_DAT[1:0]
GPI3_DAT[1:0]GPI2_DAT[1:0]GPI1_DAT[1:0]GPI0_DAT[1:0]
08hGPIA_GPIB_DATA0000hRESERVEDGPI1A_DAT[1:0]GPI0A_DAT[1:0]
RESERVEDGPI1B_DAT[1:0]GPI0B_DAT[1:0]
09hCONVERSION_CTRL0000hRESERVEDSTARTARESERVEDSTARTBRESERVEDSTOPARESERVEDSTOPB
RESERVEDSEQ2A_STARTRESERVEDSEQ2A_STOPRESERVED
10hSEQ2A_STEP0_DATA0000hSEQ2A_STEP0_DAT[15:0]
SEQ2A_STEP0_DAT[15:0]
11hSEQ2A_STEP1_DATA0000hSEQ2A_STEP1_DAT[15:0]
SEQ2A_STEP1_DAT[15:0]
12hSEQ2A_STEP2_DATA0000hSEQ2A_STEP2_DAT[15:0]
SEQ2A_STEP2_DAT[15:0]
13hSEQ2A_STEP3_DATA0000hSEQ2A_STEP3_DAT[15:0]
SEQ2A_STEP3_DAT[15:0]
14hSEQ2A_STEP4_DATA0000hSEQ2A_STEP4_DAT[15:0]
SEQ2A_STEP4_DAT[15:0]
15hSEQ2A_STEP5_DATA0000hSEQ2A_STEP5_DAT[15:0]
SEQ2A_STEP5_DAT[15:0]
16hSEQ2A_STEP6_DATA0000hSEQ2A_STEP6_DAT[15:0]
SEQ2A_STEP6_DAT[15:0]
17hSEQ2A_STEP7_DATA0000hSEQ2A_STEP7_DAT[15:0]
SEQ2A_STEP7_DAT[15:0]
18hSEQ2A_STEP8_DATA0000hSEQ2A_STEP8_DAT[15:0]
SEQ2A_STEP8_DAT[15:0]
19hSEQ2A_STEP9_DATA0000hSEQ2A_STEP9_DAT[15:0]
SEQ2A_STEP9_DAT[15:0]
1AhSEQ2A_STEP10_DATA0000hSEQ2A_STEP10_DAT[15:0]
SEQ2A_STEP10_DAT[15:0]
1BhSEQ2A_STEP11_DATA0000hSEQ2A_STEP11_DAT[15:0]
SEQ2A_STEP11_DAT[15:0]
1ChSEQ2A_STEP12_DATA0000hSEQ2A_STEP12_DAT[15:0]
SEQ2A_STEP12_DAT[15:0]
1DhSEQ2A_STEP13_DATA0000hSEQ2A_STEP13_DAT[15:0]
SEQ2A_STEP13_DAT[15:0]
1EhSEQ2A_STEP14_DATA0000hSEQ2A_STEP14_DAT[15:0]
SEQ2A_STEP14_DAT[15:0]
1FhSEQ2A_STEP15_DATA0000hSEQ2A_STEP15_DAT[15:0]
SEQ2A_STEP15_DAT[15:0]
SECTION 1
40hDEVICE_MONITOR_CFG0000hREG_MAP1_CRC_ENCRC_TYPESCLK_COUNTER_ENTIMEOUT_ENRESERVEDFAULT_POL
RESERVEDMHD_POLMHD_CFG[1:0]
41hSUPPLY_MONITOR_CFG10000hAVDD_OV_ENAVDD_UV_ENIOVDD_OV_ENIOVDD_UV_ENDVDD_OV_ENDVDD_UV_ENAVDD_OSC_ENIOVDD_OSC_EN
DVDD_OSC_ENAVDD_OTW_ENIOVDD_OTW_ENAVDD_CL_ENIOVDD_CL_ENAGNDA_DISC_ENAGNDB_DISC_ENDGND_DISC_EN
42hSUPPLY_MONITOR_CFG210F0hRESERVEDIOVDD_OV_THIOVDD_UV_THRESERVED
AVDD_OTW_CFG[1:0]IOVDD_OTW_CFG[1:0]RESERVED
43hCLOCK_MONITOR_CFG0000hRESERVED
RESERVEDMCLK_MON_ENOSCD_WD_ENMCLK_WD_EN
44hSUPPLY_MONITOR_DIAGNOSTIC_CFG0000hAVDD_OV_DIAG_ENAVDD_UV_DIAG_ENIOVDD_OV_DIAG_ENIOVDD_UV_DIAG_ENDVDD_OV_DIAG_ENDVDD_UV_DIAG_ENAVDD_OSC_DIAG_ENIOVDD_OSC_DIAG_EN
DVDD_OSC_DIAG_ENRESERVEDAGNDA_DISC_DIAG_ENAGNDB_DISC_DIAG_ENDGND_DISC_DIAG_EN
45hCLOCK_MONITOR_DIAGNOSTIC_CFG0000hSPARE[11:0]
SPARE[11:0]MCLK_HI_DIAG_ENMCLK_LO_DIAG_ENOSCD_WD_DIAG_ENMCLK_WD_DIAG_EN
46hDIGITAL_MONITOR_DIAGNOSTIC_CFG0000hRESERVEDMEM_MAP_CRC_DIAG[1:0]
RESERVEDGPIOA_DIAG_ENGPIOB_DIAG_ENGPIO_DIAG_EN
47hSUPPLY_FAULT_MASK0000hAVDD_OV_MASKAVDD_UV_MASKIOVDD_OV_MASKIOVDD_UV_MASKDVDD_OV_MASKDVDD_UV_MASKAVDD_OSC_MASKIOVDD_OSC_MASK
DVDD_OSC_MASKAVDD_OTW_MASKIOVDD_OTW_MASKAVDD_CL_MASKIOVDD_CL_MASKAGNDA_DISC_MASKAGNDB_DISC_MASKDGND_DISC_MASK
48hCLOCK_FAULT_MASK0000hRESERVED
RESERVEDMCLK_FAULT_MASKOSCD_WD_MASKMCLK_WD_MASK
49hDIGITAL_FAULT_MASK0000hREG_MAP1_CRC_FAULT_MASKREG_MAP2_CRC_FAULT_MASKREG_MAP3_CRC_FAULT_MASKRESERVEDMEM_MAP_CRC_FAULT_MASKRESERVED
RESERVED
4AhOCC_FAULT_MASK0000hRESERVED
RESERVEDOCCA_HT_MASKOCCA_LT_MASKOCCB_HT_MASKOCCB_LT_MASK
4BhFAULT_PIN_MASK0780hRESERVEDSUPPLY_FAULT_MASKCLOCK_FAULT_MASKDIGITAL_FAULT_MASKOCC_FAULT_MASKSPI_CRC_FAULT_MASKSPI_TIMEOUT_MASKSCLK_COUNT_FAULT_MASK
REG_ACCESS_FAULT_MASKRESERVED
4ChDEVICE_CFG0000hRESERVEDDRDY_CTRLRESERVEDCLK_SOURCEWORD_LENGTHRESERVEDOP_MODE[1:0]
RESERVED
4DhGPIO_CFG0000hRESERVEDGPIO4_FMTGPIO3_FMTGPIO2_FMTGPIO1_FMTGPIO0_FMTGPIO4_DIRGPIO3_DIR
GPIO2_DIRGPIO1_DIRGPIO0_DIRGPIO4_SRCGPIO3_SRCGPIO2_SRCRESERVEDGPIO0_SRC
4EhGPO_DATA0000hSPARE[10:0]
SPARE[10:0]GPO4_DATGPO3_DATGPO2_DATGPO1_DATGPO0_DAT
4FhGPIO0_LL_PWM_CFG007FhGPIO0_PWM_TB[1:0]GPIO0_LL_PWM_HC[6:0]
GPIO0_LL_PWM_HC[6:0]GPIO0_LL_PWM_LC[6:0]
50hGPIO0_LH_PWM_CFG3F80hRESERVEDGPIO0_LH_PWM_HC[6:0]
GPIO0_LH_PWM_HC[6:0]GPIO0_LH_PWM_LC[6:0]
51hGPIO1_LL_PWM_CFG007FhGPIO1_PWM_TB[1:0]GPIO1_LL_PWM_HC[6:0]
GPIO1_LL_PWM_HC[6:0]GPIO1_LL_PWM_LC[6:0]
52hGPIO1_LH_PWM_CFG3F80hRESERVEDGPIO1_LH_PWM_HC[6:0]
GPIO1_LH_PWM_HC[6:0]GPIO1_LH_PWM_LC[6:0]
53hGPIO2_LL_PWM_CFG007FhGPIO2_PWM_TB[1:0]GPIO2_LL_PWM_HC[6:0]
GPIO2_LL_PWM_HC[6:0]GPIO2_LL_PWM_LC[6:0]
54hGPIO2_LH_PWM_CFG3F80hRESERVEDGPIO2_LH_PWM_HC[6:0]
GPIO2_LH_PWM_HC[6:0]GPIO2_LH_PWM_LC[6:0]
55hGPIO3_LL_PWM_CFG007FhGPIO3_PWM_TB[1:0]GPIO3_LL_PWM_HC[6:0]
GPIO3_LL_PWM_HC[6:0]GPIO3_LL_PWM_LC[6:0]
56hGPIO3_LH_PWM_CFG3F80hRESERVEDGPIO3_LH_PWM_HC[6:0]
GPIO3_LH_PWM_HC[6:0]GPIO3_LH_PWM_LC[6:0]
57hGPIO4_LL_PWM_CFG007FhGPIO4_PWM_TB[1:0]GPIO4_LL_PWM_HC[6:0]
GPIO4_LL_PWM_HC[6:0]GPIO4_LL_PWM_LC[6:0]
58hGPIO4_LH_PWM_CFG3F80hRESERVEDGPIO4_LH_PWM_HC[6:0]
GPIO4_LH_PWM_HC[6:0]GPIO4_LH_PWM_LC[6:0]
59hSPARE_59h5555hSPARE[15:0]
SPARE[15:0]
7EhREGISTER_MAP1_CRC0000hREG_MAP1_CRC_VALUE[15:0]
REG_MAP1_CRC_VALUE[15:0]
SECTION 2
80hREGMAP2_TDACA_CFG0000hREG_MAP2_CRC_ENRESERVED
RESERVEDTDACA_VALUE[2:0]
81hGPIOA_CFG8000hRESERVEDSPARE[2:0]GPIO1A_FMTGPIO0A_FMTGPIO1A_DIRGPIO0A_DIR
GPIO1A_PWM_TB[1:0]GPIO0A_PWM_TB[1:0]SPARE[1:0]GPO1A_DATGPO0A_DAT
82hADC1A_CFG10400hRESERVEDCONV_MODE1AOSR1A[2:0]
RESERVEDGC1A_ENGC1A_DELAY[2:0]
83hADC1A_CFG28010hADC1A_ENRESERVEDGAIN1A[1:0]MUX1A[1:0]
RESERVEDOWD1A_SOURCE_MUXOWD1A_SINK_MUXOWD1A_SOURCE_VALUE[1:0]OWD1A_SINK_VALUE[1:0]
84hADC1A_OCAL_MSB0000hOCAL1A[23:8]
OCAL1A[23:8]
85hADC1A_OCAL_LSB0000hOCAL1A[7:0]
RESERVED
86hADC1A_GCAL0000hGCAL1A[15:0]
GCAL1A[15:0]
87hOCCA_CFG0000hOCCA_ENOCCA_POLRESERVEDOCCA_NUM[4:0]
RESERVED
88hOCCA_HIGH_THRESHOLD7FFFhOCCA_HIGH_TH[15:0]
OCCA_HIGH_TH[15:0]
89hOCCA_LOW_THRESHOLD8000hOCCA_LOW_TH[15:0]
OCCA_LOW_TH[15:0]
8AhSPARE_8Ah5555hSPARE[15:0]
SPARE[15:0]
8BhADC2A_CFG18010hADC2A_ENRESERVEDVCMA_ENOWD2A_SOURCE_MUX[2:0]
OWD2A_SOURCE_MUX[2:0]OWD2A_SINK_MUX[2:0]OWD2A_SOURCE_VALUE[1:0]OWD2A_SINK_VALUE[1:0]
8ChADC2A_CFG20000hSEQ2A_MODE[1:0]RESERVEDMUX2A_DELAY[2:0]
RESERVEDOSR2A[1:0]
8DhSPARE_8Dh0000hRESERVED
SPARE[7:0]
8EhADC2A_OCAL0000hOCAL2A[15:0]
OCAL2A[15:0]
8FhADC2A_GCAL0000hGCAL2A[15:0]
GCAL2A[15:0]
90hSEQ2A_STEP0_CFG0000hSEQ2A_STEP0_ENSEQ2A_STEP0_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP0_CH_NSEQ2A_STEP0_CH_P[3:0]
91hSEQ2A_STEP1_CFG0001hSEQ2A_STEP1_ENSEQ2A_STEP1_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP1_CH_NSEQ2A_STEP1_CH_P[3:0]
92hSEQ2A_STEP2_CFG0002hSEQ2A_STEP2_ENSEQ2A_STEP2_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP2_CH_NSEQ2A_STEP2_CH_P[3:0]
93hSEQ2A_STEP3_CFG0003hSEQ2A_STEP3_ENSEQ2A_STEP3_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP3_CH_NSEQ2A_STEP3_CH_P[3:0]
94hSEQ2A_STEP4_CFG0004hSEQ2A_STEP4_ENSEQ2A_STEP4_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP4_CH_NSEQ2A_STEP4_CH_P[3:0]
95hSEQ2A_STEP5_CFG0005hSEQ2A_STEP5_ENSEQ2A_STEP5_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP5_CH_NSEQ2A_STEP5_CH_P[3:0]
96hSEQ2A_STEP6_CFG0006hSEQ2A_STEP6_ENSEQ2A_STEP6_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP6_CH_NSEQ2A_STEP6_CH_P[3:0]
97hSEQ2A_STEP7_CFG0007hSEQ2A_STEP7_ENSEQ2A_STEP7_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP7_CH_NSEQ2A_STEP7_CH_P[3:0]
98hSEQ2A_STEP8_CFG0008hSEQ2A_STEP8_ENSEQ2A_STEP8_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP8_CH_NSEQ2A_STEP8_CH_P[3:0]
99hSEQ2A_STEP9_CFG0009hSEQ2A_STEP9_ENSEQ2A_STEP9_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP9_CH_NSEQ2A_STEP9_CH_P[3:0]
9AhSEQ2A_STEP10_CFG000AhSEQ2A_STEP10_ENSEQ2A_STEP10_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP10_CH_NSEQ2A_STEP10_CH_P[3:0]
9BhSEQ2A_STEP11_CFG000BhSEQ2A_STEP11_ENSEQ2A_STEP11_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP11_CH_NSEQ2A_STEP11_CH_P[3:0]
9ChSEQ2A_STEP12_CFG000ChSEQ2A_STEP12_ENSEQ2A_STEP12_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP12_CH_NSEQ2A_STEP12_CH_P[3:0]
9DhSEQ2A_STEP13_CFG000DhSEQ2A_STEP13_ENSEQ2A_STEP13_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP13_CH_NSEQ2A_STEP13_CH_P[3:0]
9EhSEQ2A_STEP14_CFG000EhSEQ2A_STEP14_ENSEQ2A_STEP14_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP14_CH_NSEQ2A_STEP14_CH_P[3:0]
9FhSEQ2A_STEP15_CFG000FhSEQ2A_STEP15_ENSEQ2A_STEP15_GAIN[1:0]RESERVED
RESERVEDSEQ2A_STEP15_CH_NSEQ2A_STEP15_CH_P[3:0]
A0hSPARE_A0h0210hRESERVEDSPARE[1:0]RESERVED
RESERVEDSPARE[1:0]RESERVED
A1hSPARE_A1h0000hSPARE[15:0]
SPARE[15:0]
A2hSPARE_A2h0000hSPARE[7:0]
RESERVED
A3hSPARE_A3h0000hSPARE[15:0]
SPARE[15:0]
BEhREGISTER_MAP2_CRC0000hREG_MAP2_CRC_VALUE[15:0]
REG_MAP2_CRC_VALUE[15:0]
SECTION 3
C0hREGMAP3_TDACB_CFG0000hREG_MAP3_CRC_ENRESERVED
RESERVEDTDACB_VALUE[2:0]
C1hGPIOB_CFG8000hRESERVEDSPARE[2:0]GPIO1B_FMTGPIO0B_FMTGPIO1B_DIRGPIO0B_DIR
GPIO1B_PWM_TB[1:0]GPIO0B_PWM_TB[1:0]SPARE[1:0]GPO1B_DATGPO0B_DAT
C2hADC1B_CFG10400hRESERVEDCONV_MODE1BOSR1B[2:0]
RESERVEDGC1B_ENGC1B_DELAY[2:0]
C3hADC1B_CFG28010hADC1B_ENRESERVEDGAIN1B[1:0]MUX1B[1:0]
RESERVEDOWD1B_SOURCE_MUXOWD1B_SINK_MUXOWD1B_SOURCE_VALUE[1:0]OWD1B_SINK_VALUE[1:0]
C4hADC1B_OCAL_MSB0000hOCAL1B[23:8]
OCAL1B[23:8]
C5hADC1B_OCAL_LSB0000hOCAL1B[7:0]
RESERVED
C6hADC1B_GCAL0000hGCAL1B[15:0]
GCAL1B[15:0]
C7hOCCB_CFG0000hOCCB_ENOCCB_POLRESERVEDOCCB_NUM[4:0]
RESERVED
C8hOCCB_HIGH_THRESHOLD7FFFhOCCB_HIGH_TH[15:0]
OCCB_HIGH_TH[15:0]
C9hOCCB_LOW_THRESHOLD8000hOCCB_LOW_TH[15:0]
OCCB_LOW_TH[15:0]
CAhSPARE_CAh5555hSPARE[15:0]
SPARE[15:0]
CBhSPARE_CBh0010hRESERVEDSPARE[6:0]
SPARE[6:0]RESERVED
CChSPARE_CCh0000hSPARE[1:0]RESERVEDSPARE[2:0]
RESERVEDSPARE[1:0]
CDhSPARE_CDh0000hRESERVED
SPARE[7:0]
CEhSPARE_CEh0000hSPARE[15:0]
SPARE[15:0]
CFhSPARE_CFh0000hSPARE[15:0]
SPARE[15:0]
D0hSPARE_D0h0000hSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
D1hSPARE_D1h0001hSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
D2hSPARE_D2h0002hSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
D3hSPARE_D3h0003hSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
D4hSPARE_D4h0004hSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
D5hSPARE_D5h0005hSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
D6hSPARE_D6h0006hSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
D7hSPARE_D7h0007hSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
D8hSPARE_D8h0008hSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
D9hSPARE_D9h0009hSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
DAhSPARE_DAh000AhSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
DBhSPARE_DBh000BhSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
DChSPARE_DCh000ChSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
DDhSPARE_DDh000DhSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
DEhSPARE_DEh000EhSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
DFhSPARE_DFh000FhSPARE[2:0]RESERVED
RESERVEDSPARE[4:0]
E0hSPARE_E0h0210hRESERVEDSPARE[1:0]RESERVED
RESERVEDSPARE[1:0]RESERVED
E1hSPARE_E1h0000hSPARE[15:0]
SPARE[15:0]
E2hSPARE_E2h0000hSPARE[7:0]
RESERVED
E3hSPARE_E3h0000hSPARE[15:0]
SPARE[15:0]
FEhREGISTER_MAP3_CRC0000hREG_MAP3_CRC_VALUE[15:0]
REG_MAP3_CRC_VALUE[15:0]

8.6.1.1 ID Register (Address = 00h) [Reset = X]

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Figure 8-46 ID Register
15141312111098
REV[7:0]
R-X
76543210
ADC_COUNT[2:0]DEVICE_ID[4:0]
R-011bR-X
Table 8-26 ID Register Field Descriptions
BitFieldTypeResetDescription
15:8REV[7:0]RXRevision ID
Values are subject to change without notice
7:5ADC_COUNT[2:0]R011bADC count

011b = 3 (ADC1A, ADC1B, ADC2A)
4:0DEVICE_ID[4:0]RXDevice ID
Values are subject to change without notice

8.6.1.2 STATUS_MSB Register (Address = 01h) [Reset = 7FC8h]

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Figure 8-47 STATUS_MSB Register
15141312111098
RESETnSUPPLY_FAULTnCLOCK_FAULTnDIGITAL_FAULTnOCC_FAULTnSPI_CRC_FAULTnSPI_TIMEOUTnSCLK_COUNT_FAULTn
R/W-0bR/W-1bR/W-1bR/W-1bR/W-1bR-1bR-1bR-1b
76543210
REG_ACCESS_FAULTnCOMMAND_RESPONSE[3:0]LOCKCLOCKMODE
R-1bR-1001bR-0bR-0bR-0b
Table 8-27 STATUS_MSB Register Field Descriptions
BitFieldTypeResetDescription
15RESETnR/W0bRESET flag
Indicates a device reset occurred. Write 1b to clear this bit to 1b.
0b = Reset occurred
1b = No reset occurred
14SUPPLY_FAULTnR/W1bSupply fault flag
Indicates that one or more of the unmasked supply fault flags in the SUPPLY_STATUS register is set. Write 1b to clear this bit to 1b after all set unmasked supply fault flags are cleared.
0b = One or more of the unmasked supply fault flags is set
1b = None of the unmasked supply fault flags are set
13CLOCK_FAULTnR/W1bClock fault flag
Indicates that one or more of the unmasked clock fault flags in the CLOCK_STATUS register is set. Write 1b to clear this bit to 1b after all set unmasked clock fault flags are cleared.
0b = One or more of the unmasked clock fault flags is set
1b = None of the unmasked supply clock fault flags are set
12DIGITAL_FAULTnR/W1bDigital fault flag
Indicates that one or more of the unmasked digital fault flags in the DIGITAL_STATUS register is set. Write 1b to clear this bit to 1b after all set unmasked digital fault flags are cleared.
0b = One or more of the unmasked digital fault flags is set
1b = None of the unmasked digital fault flags are set
11OCC_FAULTnR/W1bOvercurrent comparator fault flag
Indicates that one or more of the unmasked overcurrent comparator fault flags in the OCC_STATUS register is set. Write 1b to clear this bit to 1b after all set unmasked overcurrent comparator fault flags are cleared.
0b = One or more of the unmasked overcurrent comparator fault flags is set
1b = None of the unmasked overcurrent comparator fault flags are set
10SPI_CRC_FAULTnR1bSPI CRC fault flag
Indicates an SPI CRC fault occurred in the previous SPI frame. This bit clears automatically to 1b in each new SPI frame.
0b = SPI CRC fault occurred
1b = No SPI CRC fault occurred
9SPI_TIMEOUTnR1bSPI timeout fault flag
Indicates an SPI timeout fault occurred in the previous SPI frame. This bit clears automatically to 1b in each new SPI frame.
0b = SPI timeout fault occurred
1b = No SPI timeout fault occurred
8SCLK_COUNT_FAULTnR1bSCLK counter fault flag
Indicates an SCLK counter fault occurred in the previous SPI frame (that is, fewer or more SCLKs than required for the previous frame were sent). This bit clears automatically to 1b in each new SPI frame.
0b = SCLK counter fault occurred
1b = No SCLK counter fault occurred
7REG_ACCESS_FAULTnR1bRegister access fault flag
Indicates a read or write access to an invalid register address (register address FFh or beyond) occurred. This flag sets to 0b in the subsequent frame following the frame where a read or write operation to a register with an invalid register address was attempted. This bit clears automatically to 1b in each new SPI frame.
0b = Register access fault occurred
1b = No register access fault occurred
6:3COMMAND_RESPONSE[3:0]R1001bCommand response indication
Indicates which command was executed in the previous SPI frame.
0000b = Invalid response that does not occur under normal circumstances. Can indicate a stuck-at SDO signal or that the device is held in reset.
0001b = NULL command
0010b = LOCK command
0011b = UNLOCK command
0100b = RREG command
0101b = NULL command (because a NULL command was correctly sent as the second frame after a RREG command). This response serves as the frame counter for the two-frame RREG command.
0110b = WREG command
0111b = Invalid response that does not occur under normal circumstances.
1000b = Invalid response that does not occur under normal circumstances.
1001b = NULL command (first frame after power-up or reset). This response is only sent in the first frame after reset or power-up, the second frame has the response based on the command sent in the first frame.
1010b = NULL command (resulting from one of the following errors: a timeout occurred before a complete command CRC was received, insufficient SCLKs were sent to complete a command, a CRC mismatch between the command word and command CRC word, or a CRC mismatch between data words and the data CRC word in a WREG command). For the NULL, RREG, LOCK, and UNLOCK commands, the command and command CRC words must be sent to complete the command. For the RESET command, the STATUS word, all ADC data words, and the output CRC word must be read to complete the command. For the WREG command, the command and command CRC words, as well as the data and data CRC words must be sent to complete the command.
1011b = NULL command (resulting from an invalid command word with a matching CRC between the command word and command CRC word).
1100b = NULL command (resulting from a command other than the NULL command was sent in the second frame after the RREG command and ignored). This response serves as the frame counter for the two-frame RREG command.
1101b = NULL command (the RESET or WREG commands are ignored because the device is locked).
1110b = Invalid response that does not occur under normal circumstances.
1111b = Invalid response that does not occur under normal circumstances. Can indicate a stuck-at SDO signal.
2LOCKR0bLock state indication
Indicates if the device is locked or unlocked.
0b = Device is unlocked
1b = Device is locked
1CLOCKR0bClock source indication
Indicates which clock source the device is currently using.
0b = Internal oscillator
1b = External clock
0MODER0bOperating mode indication
Indicates which operating mode the device is currently in.
0b = Active mode
1b = Standby or power-down mode

8.6.1.3 STATUS_LSB Register (Address = 02h) [Reset = 0000h]

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Figure 8-48 STATUS_LSB Register
15141312111098
SEQ2A_COUNT[1:0]RESERVEDCONV1A_COUNT[1:0]CONV1B_COUNT[1:0]
R-00bR-00bR-00bR-00b
76543210
RESERVEDSEQ2A_ACTIVERESERVED
R-000000bR-0bR-0b
Table 8-28 STATUS_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:14SEQ2A_COUNT[1:0]R00bADC2A sequence counter
Circular counter that increments each time a new sequence on ADC2A completes. This counter resets to 00b when ADC2A is disabled, when the device is put in standby or power-down mode, or after a device reset.
13:12RESERVEDR00bReserved
Always reads 00b.
11:10CONV1A_COUNT[1:0]R00bADC1A conversion counter
Circular counter that increments each time a new conversion on ADC1A completes. This counter resets to 00b when ADC1A is disabled, when the device is put in standby or power-down mode, or after a device reset.
9:8CONV1B_COUNT[1:0]R00bADC1B conversion counter
Circular counter that increments each time a new conversion on ADC1B completes. This counter resets to 00b when ADC1B is disabled, when the device is put in standby or power-down mode, or after a device reset.
7:2RESERVEDR000000bReserved
Always reads 000000b.
1SEQ2A_ACTIVER0bADC2A sequence in progress indication
Indicates that a sequence on ADC2A is currently in progress. Changes to registers from address 8Ch to 9Fh of ADC2A must only be made when ADC2A is disabled.
0b = No sequence in progress
1b = Sequence in progress
0RESERVEDR0bReserved
Always reads 0b.

8.6.1.4 SUPPLY_STATUS Register (Address = 03h) [Reset = FFFFh]

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Figure 8-49 SUPPLY_STATUS Register
15141312111098
AVDD_OVnAVDD_UVnIOVDD_OVnIOVDD_UVnDVDD_OVnDVDD_UVnAVDD_OSCnIOVDD_OSCn
R/W-1bR/W-1bR/W-1bR/W-1bR/W-1bR/W-1bR/W-1bR/W-1b
76543210
DVDD_OSCnAVDD_OTWnIOVDD_OTWnAVDD_CLnIOVDD_CLnAGNDA_DISCnAGNDB_DISCnDGND_DISCn
R/W-1bR/W-1bR/W-1bR/W-1bR/W-1bR/W-1bR/W-1bR/W-1b
Table 8-29 SUPPLY_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15AVDD_OVnR/W1bAVDD overvoltage fault flag
Indicates the AVDD supply voltage exceeded the AVDD overvoltage threshold. See the AVDD monitor description for details regarding the AVDD LDO shutdown during overvoltage. Write 1b to clear this bit to 1b.
0b = Overvoltage fault occurred
1b = No overvoltage fault occurred
14AVDD_UVnR/W1bAVDD undervoltage fault flag
Indicates the AVDD supply voltage dropped below the AVDD undervoltage threshold. Write 1b to clear this bit to 1b.
0b = Undervoltage fault occurred
1b = No undervoltage fault occurred
13IOVDD_OVnR/W1bIOVDD overvoltage fault flag
Indicates the IOVDD supply voltage exceeded the IOVDD overvoltage threshold. See the IOVDD monitor description for details regarding the IOVDD LDO shutdown during overvoltage. Write 1b to clear this bit to 1b.
0b = Overvoltage fault occurred
1b = No overvoltage fault occurred
12IOVDD_UVnR/W1bIOVDD undervoltage fault flag
Indicates the IOVDD supply voltage dropped below the IOVDD undervoltage threshold. Write 1b to clear this bit to 1b.
0b = Undervoltage fault occurred
1b = No undervoltage fault occurred
11DVDD_OVnR/W1bDVDD overvoltage fault flag
Indicates the DVDD supply voltage exceeded the DVDD overvoltage threshold. See the DVDD monitor description for details regarding the DVDD LDO shutdown during overvoltage. Write 1b to clear this bit to 1b.
0b = Overvoltage fault occurred
1b = No overvoltage fault occurred
10DVDD_UVnR/W1bDVDD undervoltage fault flag
Indicates the DVDD supply voltage dropped below the DVDD undervoltage threshold. Write 1b to clear this bit to 1b.
0b = Undervoltage fault occurred
1b = No undervoltage fault occurred
9AVDD_OSCnR/W1bAVDD oscillation fault flag
Indicates the AVDD supply voltage is oscillating. Write 1b to clear this bit to 1b.
0b = Oscillation fault occurred
1b = No oscillation fault occurred
8IOVDD_OSCnR/W1bIOVDD oscillation fault flag
Indicates the IOVDD supply voltage is oscillating. Write 1b to clear this bit to 1b.
0b = Oscillation fault occurred
1b = No oscillation fault occurred
7DVDD_OSCnR/W1bDVDD oscillation fault flag
Indicates the DVDD supply voltage is oscillating. Write 1b to clear this bit to 1b.
0b = Oscillation fault occurred
1b = No oscillation fault occurred
6AVDD_OTWnR/W1bAVDD overtemperature warning flag
Indicates the AVDD LDO temperature exceeded the AVDD overtemperature warning threshold. Write 1b to clear this bit to 1b.
0b = Overtemperature warning
1b = No overtemperature warning
5IOVDD_OTWnR/W1bIOVDD overtemperature warning flag
Indicates the IOVDD LDO temperature exceeded the IOVDD overtemperature warning threshold. Write 1b to clear this bit to 1b.
0b = Overtemperature warning
1b = No overtemperature warning
4AVDD_CLnR/W1bAVDD current limit flag
Indicates the AVDD LDO current limit is active. Write 1b to clear this bit to 1b.
0b = Current limit
1b = No current limit
3IOVDD_CLnR/W1bIOVDD current limit flag
Indicates the IOVDD LDO current limit is active. Write 1b to clear this bit to 1b.
0b = Current limit
1b = No current limit
2AGNDA_DISCnR/W1bAGNDA pin disconnect detection flag
Indicates the AGNDA pin is disconnected. Write 1b to clear this bit to 1b.
0b = AGNDA pin disconnected
1b = AGNDA pin connected
1AGNDB_DISCnR/W1bAGNDB pin disconnect detection flag
Indicates the AGNDB pin is disconnected. Write 1b to clear this bit to 1b.
0b = AGNDB pin disconnected
1b = AGNDB pin connected
0DGND_DISCnR/W1bDGND pin disconnect detection flag
Indicates the DGND pin is disconnected. Write 1b to clear this bit to 1b.
0b = DGND pin disconnected
1b = DGND pin connected

8.6.1.5 CLOCK_STATUS Register (Address = 04h) [Reset = FC07h]

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Figure 8-50 CLOCK_STATUS Register
15141312111098
RESERVED
R-1111110000000b
76543210
RESERVEDMCLK_FAULTnOSCD_WDnMCLK_WDn
R-1111110000000bR/W-1bR/W-1bR/W-1b
Table 8-30 CLOCK_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15:3RESERVEDR1111110000000bReserved
Always reads 1111110000000b.
2MCLK_FAULTnR/W1bMCLK frequency too high or too low fault flag
Indicates the main clock frequency of the selected clock source either exceeded the clock frequency high threshold or dropped below the clock frequency low threshold. Write 1b to clear this bit to 1b.
0b = MCLK frequency too high or too low fault occurred
1b = No MCLK frequency too high or too low fault occurred
1OSCD_WDnR/W1bDiagnostic oscillator watchdog fault flag
Indicates a diagnostic oscillator watchdog fault occurred. Write 1b to clear this bit to 1b.
0b = Watchdog fault occurred
1b = No watchdog fault occurred
0MCLK_WDnR/W1bMain clock watchdog fault flag
Indicates a main clock watchdog fault occurred. Write 1b to clear this bit to 1b.
0b = Watchdog fault occurred
1b = No watchdog fault occurred

8.6.1.6 DIGITAL_STATUS Register (Address = 05h) [Reset = EC00h]

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Figure 8-51 DIGITAL_STATUS Register
15141312111098
REG_MAP1_CRC_FAULTnREG_MAP2_CRC_FAULTnREG_MAP3_CRC_FAULTnRESERVEDMEM_MAP_CRC_FAULTnOTP_BANKRESERVED
R/W-1bR/W-1bR/W-1bR-0bR/W-1bR-1bR-0000000000b
76543210
RESERVED
R-0000000000b
Table 8-31 DIGITAL_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15REG_MAP1_CRC_FAULTnR/W1bRegister map section 1 CRC fault flag
Indicates a register map CRC fault in section 1 (register address space from 40h to 59h) occurred. Write 1b to clear this bit to 1b.
0b = Register map CRC fault occurred
1b = No register map CRC fault occurred
14REG_MAP2_CRC_FAULTnR/W1bRegister map section 2 CRC fault flag
Indicates a register map CRC fault in section 2 (register address space from 80h to A3h) occurred. Write 1b to clear this bit to 1b.
0b = Register map CRC fault occurred
1b = No register map CRC fault occurred
13REG_MAP3_CRC_FAULTnR/W1bRegister map section 3 CRC fault flag
Indicates a register map CRC fault in section 3 (register address space from C0h to E3h) occurred. Write 1b to clear this bit to 1b.
0b = Register map CRC fault occurred
1b = No register map CRC fault occurred
12RESERVEDR0bReserved
Always reads 0b.
11MEM_MAP_CRC_FAULTnR/W1bMemory map CRC fault flag
Indicates a memory map CRC fault in the internal memory occurred. Write 1b to clear this bit to 1b. Reset the device in case the flag continues to set to 0b.
0b = Memory map CRC fault occurred
1b = No memory map CRC fault occurred
10OTP_BANKR1bOTP bank indication
Indicates which OTP bank the device selected after reset. The OTP_BANK bit does not trigger the DIGITAL_FAULTn bit in the STATUS_MSB register. Reset the device in case the flag indicates that the backup OTP bank is used.
0b = Backup OTP bank (bank 1)
1b = Primary OTP bank (bank 0)
9:0RESERVEDR0000000000bReserved
Always reads 0000000000b.

8.6.1.7 OCC_STATUS Register (Address = 06h) [Reset = 000Fh]

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Figure 8-52 OCC_STATUS Register
15141312111098
RESERVED
R-000000000000b
76543210
RESERVEDOCCA_HTnOCCA_LTnOCCB_HTnOCCB_LTn
R-000000000000bR/W-1bR/W-1bR/W-1bR/W-1b
Table 8-32 OCC_STATUS Register Field Descriptions
BitFieldTypeResetDescription
15:4RESERVEDR000000000000bReserved
Always reads 000000000000b.
3OCCA_HTnR/W1bADC1A overcurrent comparator high threshold fault flag
Indicates the ADC1A digital fast filter output exceeded the set high threshold for the set amount of conversions. Write 1b to clear this bit to 1b.
0b = High threshold fault occurred
1b = No high threshold fault occurred
2OCCA_LTnR/W1bADC1A overcurrent comparator low threshold fault flag
Indicates the ADC1A digital fast filter output dropped below the set low threshold for the set amount of conversions. Write 1b to clear this bit to 1b.
0b = Low threshold fault occurred
1b = No low threshold fault occurred
1OCCB_HTnR/W1bADC1B overcurrent comparator high threshold fault flag
Indicates the ADC1B digital fast filter output exceeded the set high threshold for the set amount of conversions. Write 1b to clear this bit to 1b.
0b = High threshold fault occurred
1b = No high threshold fault occurred
0OCCB_LTnR/W1bADC1B overcurrent comparator low threshold fault flag
Indicates the ADC1B digital fast filter output dropped below the set low threshold for the set amount of conversions. Write 1b to clear this bit to 1b.
0b = Low threshold fault occurred
1b = No low threshold fault occurred

8.6.1.8 GPI_DATA Register (Address = 07h) [Reset = 0000h]

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Figure 8-53 GPI_DATA Register
15141312111098
RESERVEDGPI4_DAT[1:0]
R-000000bR-00b
76543210
GPI3_DAT[1:0]GPI2_DAT[1:0]GPI1_DAT[1:0]GPI0_DAT[1:0]
R-00bR-00bR-00bR-00b
Table 8-33 GPI_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR000000bReserved
Always reads 000000b.
9:8GPI4_DAT[1:0]R00bGPIO4 data readback
Readback value of GPIO4 when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
7:6GPI3_DAT[1:0]R00bGPIO3 data readback
Readback value of GPIO3 when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
5:4GPI2_DAT[1:0]R00bGPIO2 data readback
Readback value of GPIO2 when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
3:2GPI1_DAT[1:0]R00bGPIO1 data readback
Readback value of GPIO1 when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
1:0GPI0_DAT[1:0]R00bGPIO0 data readback
Readback value of GPIO0 when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)

8.6.1.9 GPIA_GPIB_DATA Register (Address = 08h) [Reset = 0000h]

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Figure 8-54 GPIA_GPIB_DATA Register
15141312111098
RESERVEDGPI1A_DAT[1:0]GPI0A_DAT[1:0]
R-0000bR-00bR-00b
76543210
RESERVEDGPI1B_DAT[1:0]GPI0B_DAT[1:0]
R-0000bR-00bR-00b
Table 8-34 GPIA_GPIB_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0000bReserved
Always reads 0000b.
11:10GPI1A_DAT[1:0]R00bGPIO1A data readback
Readback value of GPIO1A when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
9:8GPI0A_DAT[1:0]R00bGPIO0A data readback
Readback value of GPIO0A when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
7:4RESERVEDR0000bReserved
Always reads 0000b.
3:2GPI1B_DAT[1:0]R00bGPIO1B data readback
Readback value of GPIO1B when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)
1:0GPI0B_DAT[1:0]R00bGPIO0B data readback
Readback value of GPIO0B when configured as a digital input or output.
00b = Low (static low or PWM with a low period >66.6%)
01b = Weak low (PWM with a low period ≥50% but ≤66.6%)
10b = Weak high (PWM with a high period >50% but ≤66.6%)
11b = High (static high or PWM with a high period >66.6%)

8.6.1.10 CONVERSION_CTRL Register (Address = 09h) [Reset = 0000h]

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Figure 8-55 CONVERSION_CTRL Register
15141312111098
RESERVEDSTARTARESERVEDSTARTBRESERVEDSTOPARESERVEDSTOPB
R-0bR/W-0bR-0bR/W-0bR-0bR/W-0bR-0bR/W-0b
76543210
RESERVEDSEQ2A_STARTRESERVEDSEQ2A_STOPRESERVED
R-0bR/W-0bR-000bR/W-0bR-00b
Table 8-35 CONVERSION_CTRL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0bReserved
Always reads 0b.
14STARTAR/W0bStart or re-start ADC1A conversions
Write 1b to start or restart conversions of enabled ADC1A. Always reads back 0b.
13RESERVEDR0bReserved
Always reads 0b.
12STARTBR/W0bStart or restart ADC1B conversions
Write 1b to start or restart conversions of enabled ADC1B. Always reads back 0b.
11RESERVEDR0bReserved
Always reads 0b.
10STOPAR/W0bStop ADC1A conversions
Write 1b to stop conversions of ADC1A in continuous-conversion mode. Ongoing conversions are allowed to complete. The STOPA bit has no effect in single-shot conversion mode. The STARTA bit takes priority over the STOPA bit if both bits are set during the same WREG command frame. The STOPA bit clears to 0b after the ongoing conversion finishes or when the STARTA bit is set before the ongoing conversion finishes, which aborts the ongoing conversion and restarts new conversions.
9RESERVEDR0bReserved
Always reads 0b.
8STOPBR/W0bStop ADC1B conversions
Write 1b to stop conversions of ADC1B in continuous-conversion mode. Ongoing conversions are allowed to complete. The STOPB bit has no effect in single-shot conversion mode. The STARTB bit takes priority over the STOPB bit if both bits are set during the same WREG command frame. The STOPB bit clears to 0b after the ongoing conversion finishes or when the STARTB bit is set before the ongoing conversion finishes, which aborts the ongoing conversion and restarts new conversions.
7RESERVEDR0bReserved
Always reads 0b.
6SEQ2A_STARTR/W0bStart ADC2A sequence
Write 1b to start or restart sequence of ADC2A. Always reads back 0b.
5:3RESERVEDR000bReserved
Always reads 000b.
2SEQ2A_STOPR/W0bStop ADC2A sequence
Write 1b to stop ADC2A sequence. A sequence in progress is allowed to finish. The SEQ2A_START bit takes priority over the SEQ2A_STOP bit if both bits are set during the same WREG command frame. The SEQ2A_STOP bit clears to 0b after the ongoing sequence finishes or when the SEQ2A_START bit is set before the ongoing sequence finishes, which aborts the ongoing sequence and restarts a new sequence.
1:0RESERVEDR00bReserved
Always reads 00b.

8.6.1.11 SEQ2A_STEP0_DATA Register (Address = 10h) [Reset = 0000h]

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Figure 8-56 SEQ2A_STEP0_DATA Register
15141312111098
SEQ2A_STEP0_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP0_DAT[15:0]
R-0000000000000000b
Table 8-36 SEQ2A_STEP0_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP0_DAT[15:0]R0000000000000000bADC2A sequence step 0 conversion data
Value provided in two's complement format.

8.6.1.12 SEQ2A_STEP1_DATA Register (Address = 11h) [Reset = 0000h]

Return to the Summary Table.

Figure 8-57 SEQ2A_STEP1_DATA Register
15141312111098
SEQ2A_STEP1_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP1_DAT[15:0]
R-0000000000000000b
Table 8-37 SEQ2A_STEP1_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP1_DAT[15:0]R0000000000000000bADC2A sequence step 1 conversion data
Value provided in two's complement format.

8.6.1.13 SEQ2A_STEP2_DATA Register (Address = 12h) [Reset = 0000h]

Return to the Summary Table.

Figure 8-58 SEQ2A_STEP2_DATA Register
15141312111098
SEQ2A_STEP2_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP2_DAT[15:0]
R-0000000000000000b
Table 8-38 SEQ2A_STEP2_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP2_DAT[15:0]R0000000000000000bADC2A sequence step 2 conversion data
Value provided in two's complement format.

8.6.1.14 SEQ2A_STEP3_DATA Register (Address = 13h) [Reset = 0000h]

Return to the Summary Table.

Figure 8-59 SEQ2A_STEP3_DATA Register
15141312111098
SEQ2A_STEP3_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP3_DAT[15:0]
R-0000000000000000b
Table 8-39 SEQ2A_STEP3_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP3_DAT[15:0]R0000000000000000bADC2A sequence step 3 conversion data
Value provided in two's complement format.

8.6.1.15 SEQ2A_STEP4_DATA Register (Address = 14h) [Reset = 0000h]

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Figure 8-60 SEQ2A_STEP4_DATA Register
15141312111098
SEQ2A_STEP4_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP4_DAT[15:0]
R-0000000000000000b
Table 8-40 SEQ2A_STEP4_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP4_DAT[15:0]R0000000000000000bADC2A sequence step 4 conversion data
Value provided in two's complement format.

8.6.1.16 SEQ2A_STEP5_DATA Register (Address = 15h) [Reset = 0000h]

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Figure 8-61 SEQ2A_STEP5_DATA Register
15141312111098
SEQ2A_STEP5_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP5_DAT[15:0]
R-0000000000000000b
Table 8-41 SEQ2A_STEP5_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP5_DAT[15:0]R0000000000000000bADC2A sequence step 5 conversion data
Value provided in two's complement format.

8.6.1.17 SEQ2A_STEP6_DATA Register (Address = 16h) [Reset = 0000h]

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Figure 8-62 SEQ2A_STEP6_DATA Register
15141312111098
SEQ2A_STEP6_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP6_DAT[15:0]
R-0000000000000000b
Table 8-42 SEQ2A_STEP6_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP6_DAT[15:0]R0000000000000000bADC2A sequence step 6 conversion data
Value provided in two's complement format.

8.6.1.18 SEQ2A_STEP7_DATA Register (Address = 17h) [Reset = 0000h]

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Figure 8-63 SEQ2A_STEP7_DATA Register
15141312111098
SEQ2A_STEP7_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP7_DAT[15:0]
R-0000000000000000b
Table 8-43 SEQ2A_STEP7_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP7_DAT[15:0]R0000000000000000bADC2A sequence step 7 conversion data
Value provided in two's complement format.

8.6.1.19 SEQ2A_STEP8_DATA Register (Address = 18h) [Reset = 0000h]

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Figure 8-64 SEQ2A_STEP8_DATA Register
15141312111098
SEQ2A_STEP8_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP8_DAT[15:0]
R-0000000000000000b
Table 8-44 SEQ2A_STEP8_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP8_DAT[15:0]R0000000000000000bADC2A sequence step 8 conversion data
Value provided in two's complement format.

8.6.1.20 SEQ2A_STEP9_DATA Register (Address = 19h) [Reset = 0000h]

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Figure 8-65 SEQ2A_STEP9_DATA Register
15141312111098
SEQ2A_STEP9_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP9_DAT[15:0]
R-0000000000000000b
Table 8-45 SEQ2A_STEP9_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP9_DAT[15:0]R0000000000000000bADC2A sequence step 9 conversion data
Value provided in two's complement format.

8.6.1.21 SEQ2A_STEP10_DATA Register (Address = 1Ah) [Reset = 0000h]

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Figure 8-66 SEQ2A_STEP10_DATA Register
15141312111098
SEQ2A_STEP10_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP10_DAT[15:0]
R-0000000000000000b
Table 8-46 SEQ2A_STEP10_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP10_DAT[15:0]R0000000000000000bADC2A sequence step 10 conversion data
Value provided in two's complement format.

8.6.1.22 SEQ2A_STEP11_DATA Register (Address = 1Bh) [Reset = 0000h]

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Figure 8-67 SEQ2A_STEP11_DATA Register
15141312111098
SEQ2A_STEP11_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP11_DAT[15:0]
R-0000000000000000b
Table 8-47 SEQ2A_STEP11_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP11_DAT[15:0]R0000000000000000bADC2A sequence step 11 conversion data
Value provided in two's complement format.

8.6.1.23 SEQ2A_STEP12_DATA Register (Address = 1Ch) [Reset = 0000h]

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Figure 8-68 SEQ2A_STEP12_DATA Register
15141312111098
SEQ2A_STEP12_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP12_DAT[15:0]
R-0000000000000000b
Table 8-48 SEQ2A_STEP12_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP12_DAT[15:0]R0000000000000000bADC2A sequence step 12 conversion data
Value provided in two's complement format.

8.6.1.24 SEQ2A_STEP13_DATA Register (Address = 1Dh) [Reset = 0000h]

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Figure 8-69 SEQ2A_STEP13_DATA Register
15141312111098
SEQ2A_STEP13_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP13_DAT[15:0]
R-0000000000000000b
Table 8-49 SEQ2A_STEP13_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP13_DAT[15:0]R0000000000000000bADC2A sequence step 13 conversion data
Value provided in two's complement format.

8.6.1.25 SEQ2A_STEP14_DATA Register (Address = 1Eh) [Reset = 0000h]

Return to the Summary Table.

Figure 8-70 SEQ2A_STEP14_DATA Register
15141312111098
SEQ2A_STEP14_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP14_DAT[15:0]
R-0000000000000000b
Table 8-50 SEQ2A_STEP14_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP14_DAT[15:0]R0000000000000000bADC2A sequence step 14 conversion data
Value provided in two's complement format.

8.6.1.26 SEQ2A_STEP15_DATA Register (Address = 1Fh) [Reset = 0000h]

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Figure 8-71 SEQ2A_STEP15_DATA Register
15141312111098
SEQ2A_STEP15_DAT[15:0]
R-0000000000000000b
76543210
SEQ2A_STEP15_DAT[15:0]
R-0000000000000000b
Table 8-51 SEQ2A_STEP15_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:0SEQ2A_STEP15_DAT[15:0]R0000000000000000bADC2A sequence step 15 conversion data
Value provided in two's complement format.

8.6.1.27 DEVICE_MONITOR_CFG Register (Address = 40h) [Reset = 0000h]

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Figure 8-72 DEVICE_MONITOR_CFG Register
15141312111098
REG_MAP1_CRC_ENCRC_TYPESCLK_COUNTER_ENTIMEOUT_ENRESERVEDFAULT_POL
R/W-0bR/W-0bR/W-0bR/W-0bR-000bR/W-0b
76543210
RESERVEDMHD_POLMHD_CFG[1:0]
R-00000bR/W-0bR/W-00b
Table 8-52 DEVICE_MONITOR_CFG Register Field Descriptions
BitFieldTypeResetDescription
15REG_MAP1_CRC_ENR/W0bRegister map section 1 CRC enable
Enables the register map CRC for section 1 (register address space from 40h to 59h).
0b = Disabled
1b = Enabled
14CRC_TYPER/W0bCRC type selection
Selects the CRC polynomial that is used for the SPI and register map CRC calculation.
0b = 16-bit CCITT
1b = 16-bit ANSI
13SCLK_COUNTER_ENR/W0bSCLK counter enable
Enables the SCLK counter.
0b = Disabled
1b = Enabled
12TIMEOUT_ENR/W0bSPI timeout enable
Enables the SPI timeout. When enabled the timeout checks that a rising edge of CSn happens within 214 tOSCD cycles after a CSn falling edge. When a timeout occurs, the remainder of the SPI frame on SDI is ignored before the rising edge of CSn. A new SPI transaction starts at the next CSn falling edge.
0b = Disabled
1b = Enabled
11:9RESERVEDR000bReserved
Always reads back 000b.
8FAULT_POLR/W0bFAULT pin polarity selection
Selects the polarity of the FAULT pin. The actual output behavior of the GPIO2/FAULT pin, when configured as a FAULT output in the GPIO2_SRC bit, depends on the GPIO2_FMT setting. A FAULT is active when any of the non-masked STATUS_MSB[14:7] bits are active.
0b = Active low. In case of a fault a logic low level is driven.
1b = Active high. In case of a fault a logic high level is driven.
7:3RESERVEDR00000bReserved
Always reads back 00000b.
2MHD_POLR/W0bMissing host detection fault pin polarity selection
Selects the polarity of the MHD pin. The actual output behavior of the GPIO0/MHD pin, when configured as an MHD output in the GPIO0_SRC bit, depends on the GPIO0_FMT setting.
0b = Active low. In case of a fault a logic low level is driven.
1b = Active high. In case of a fault a logic high level is driven.
1:0MHD_CFG[1:0]R/W00bMissing host detection configuration
Detects when the host is not communicating with the device anymore. A watchdog timer checks the time between two valid commands with a valid CRC. If a valid command with a valid CRC is not received within the watchdog time window, the host is considered missing. When the watchdog times out, the GPIO0/MHD pin is set to active. To use the missing host detection mode, configure the GPIO0/MHD pin as an output using the GPIO0_DIR bit and the source for missing host detection mode using the GPIO0_SRC bit. To reset the GPIO0/MHD output after a missing host was detected, disable the missing host detection mode by setting MHD_CFG = 00b.
00b = Disabled
01b = 5120 x tOSCD (= 0.625 ms for fOSCD = 8.192 MHz)
10b = 10240 x tOSCD (= 1.25 ms for fOSCD = 8.192 MHz)
11b = 20480 x tOSCD (= 2.5 ms for fOSCD = 8.192 MHz)

8.6.1.28 SUPPLY_MONITOR_CFG1 Register (Address = 41h) [Reset = 0000h]

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Figure 8-73 SUPPLY_MONITOR_CFG1 Register
15141312111098
AVDD_OV_ENAVDD_UV_ENIOVDD_OV_ENIOVDD_UV_ENDVDD_OV_ENDVDD_UV_ENAVDD_OSC_ENIOVDD_OSC_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
76543210
DVDD_OSC_ENAVDD_OTW_ENIOVDD_OTW_ENAVDD_CL_ENIOVDD_CL_ENAGNDA_DISC_ENAGNDB_DISC_ENDGND_DISC_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-53 SUPPLY_MONITOR_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15AVDD_OV_ENR/W0bAVDD LDO overvoltage monitor enable
Enables the AVDD LDO output overvoltage monitor.
0b = Disabled
1b = Enabled
14AVDD_UV_ENR/W0bAVDD LDO undervoltage monitor enable
Enables the AVDD LDO output undervoltage monitor.
0b = Disabled
1b = Enabled
13IOVDD_OV_ENR/W0bIOVDD LDO overvoltage monitor enable
Enables the IOVDD LDO output overvoltage monitor.
0b = Disabled
1b = Enabled
12IOVDD_UV_ENR/W0bIOVDD LDO undervoltage monitor enable
Enables the IOVDD LDO output undervoltage monitor.
0b = Disabled
1b = Enabled
11DVDD_OV_ENR/W0bDVDD LDO overvoltage monitor enable
Enables the DVDD LDO output overvoltage monitor.
0b = Disabled
1b = Enabled
10DVDD_UV_ENR/W0bDVDD LDO undervoltage monitor enable
Enables the DVDD LDO output undervoltage monitor.
0b = Disabled
1b = Enabled
9AVDD_OSC_ENR/W0bAVDD LDO oscillation monitor enable
Enables the AVDD LDO output oscillation monitor.
0b = Disabled
1b = Enabled
8IOVDD_OSC_ENR/W0bIOVDD LDO oscillation monitor enable
Enables the IOVDD LDO output oscillation monitor.
0b = Disabled
1b = Enabled
7DVDD_OSC_ENR/W0bDVDD LDO oscillation monitor enable
Enables the DVDD LDO output oscillation monitor.
0b = Disabled
1b = Enabled
6AVDD_OTW_ENR/W0bAVDD LDO overtemperature warning monitor enable
Enables the AVDD LDO overtemperature warning monitor.
0b = Disabled
1b = Enabled
5IOVDD_OTW_ENR/W0bIOVDD LDO overtemperature warning monitor enable
Enables the IOVDD LDO overtemperature warning monitor.
0b = Disabled
1b = Enabled
4AVDD_CL_ENR/W0bAVDD LDO current limit enable
Enables the AVDD LDO current limit.
0b = Disabled
1b = Enabled
3IOVDD_CL_ENR/W0bIOVDD LDO current limit enable
Enables the IOVDD LDO current limit.
0b = Disabled
1b = Enabled
2AGNDA_DISC_ENR/W0bAGNDA disconnect monitor enable
Enables the AGNDA disconnect monitor.
0b = Disabled
1b = Enabled
1AGNDB_DISC_ENR/W0bAGNDB disconnect monitor enable
Enables the AGNDB disconnect monitor.
0b = Disabled
1b = Enabled
0DGND_DISC_ENR/W0bDGND disconnect monitor enable
Enables the DGND disconnect monitor.
0b = Disabled
1b = Enabled

8.6.1.29 SUPPLY_MONITOR_CFG2 Register (Address = 42h) [Reset = 10F0h]

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Figure 8-74 SUPPLY_MONITOR_CFG2 Register
15141312111098
RESERVEDIOVDD_OV_THIOVDD_UV_THRESERVED
R-00bR/W-0bR/W-1bR-0000b
76543210
AVDD_OTW_CFG[1:0]IOVDD_OTW_CFG[1:0]RESERVED
R/W-11bR/W-11bR-0000b
Table 8-54 SUPPLY_MONITOR_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR00bReserved
Always reads back 00b.
13IOVDD_OV_THR/W0bIOVDD overvoltage threshold selection
Selects the threshold for the IOVDD LDO output overvoltage monitor.
0b = 5.7 V
1b = 3.9 V
12IOVDD_UV_THR/W1bIOVDD undervoltage threshold selection
Selects the threshold for the IOVDD LDO output undervoltage monitor.
0b = 4.3 V
1b = 2.95 V
11:8RESERVEDR0000bReserved
Always reads back 0000b.
7:6AVDD_OTW_CFG[1:0]R/W11bAVDD LDO overtemperature warning threshold selection
Selects the threshold for AVDD LDO overtemperature warning.
00b = #dash<deg#C
01b = 100°C
10b = 120°C
11b = 140°C
5:4IOVDD_OTW_CFG[1:0]R/W11bIOVDD LDO overtemperature warning threshold selection
Selects the threshold for IOVDD LDO overtemperature warning.
00b = #dash<deg#C
01b = 100°C
10b = 120°C
11b = 140°C
3:0RESERVEDR0000bReserved
Always reads back 0000b.

8.6.1.30 CLOCK_MONITOR_CFG Register (Address = 43h) [Reset = 0000h]

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Figure 8-75 CLOCK_MONITOR_CFG Register
15141312111098
RESERVEDRESERVED
R/W-000000bR-0000000b
76543210
RESERVEDMCLK_MON_ENOSCD_WD_ENMCLK_WD_EN
R-0000000bR/W-0bR/W-0bR/W-0b
Table 8-55 CLOCK_MONITOR_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved
Always write 000000b.
9:3RESERVEDR0000000bReserved
Always reads back 0000000b.
2MCLK_MON_ENR/W0bMCLK monitor enable
Enables the main clock frequency monitor.
0b = Disabled
1b = Enabled
1OSCD_WD_ENR/W0bDiagnostic oscillator watchdog enable
Enables the diagnostic oscillator watchdog.
0b = Disabled
1b = Enabled
0MCLK_WD_ENR/W0bMain clock watchdog enable
Enables the main clock watchdog.
0b = Disabled
1b = Enabled

8.6.1.31 SUPPLY_MONITOR_DIAGNOSTIC_CFG Register (Address = 44h) [Reset = 0000h]

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Figure 8-76 SUPPLY_MONITOR_DIAGNOSTIC_CFG Register
15141312111098
AVDD_OV_DIAG_ENAVDD_UV_DIAG_ENIOVDD_OV_DIAG_ENIOVDD_UV_DIAG_ENDVDD_OV_DIAG_ENDVDD_UV_DIAG_ENAVDD_OSC_DIAG_ENIOVDD_OSC_DIAG_EN
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
76543210
DVDD_OSC_DIAG_ENRESERVEDAGNDA_DISC_DIAG_ENAGNDB_DISC_DIAG_ENDGND_DISC_DIAG_EN
R/W-0bR-0000bR/W-0bR/W-0bR/W-0b
Table 8-56 SUPPLY_MONITOR_DIAGNOSTIC_CFG Register Field Descriptions
BitFieldTypeResetDescription
15AVDD_OV_DIAG_ENR/W0bAVDD LDO overvoltage monitor diagnostic enable
Enables the AVDD LDO output overvoltage monitor diagnostic. AVDD_OV_EN must be set for the diagnostic to work. The AVDD_OVn fault flag sets within tp(AVDD_OV) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
14AVDD_UV_DIAG_ENR/W0bAVDD LDO undervoltage monitor diagnostic enable
Enables the AVDD LDO output undervoltage monitor diagnostic. AVDD_UV_EN must be set for the diagnostic to work. The AVDD_UVn fault flag sets within tp(AVDD_UV) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
13IOVDD_OV_DIAG_ENR/W0bIOVDD LDO overvoltage monitor diagnostic enable
Enables the IOVDD LDO output overvoltage monitor diagnostic. IOVDD_OV_EN must be set for the diagnostic to work. The IOVDD_OVn fault flag sets within tp(IOVDD._OV) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
12IOVDD_UV_DIAG_ENR/W0bIOVDD LDO undervoltage monitor diagnostic enable
Enables the IOVDD LDO output undervoltage monitor diagnostic. IOVDD_UV_EN must be set for the diagnostic to work. The IOVDD_UVn fault flag sets within tp(IOVDD_UV) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
11DVDD_OV_DIAG_ENR/W0bDVDD LDO overvoltage monitor diagnostic enable
Enables the DVDD LDO output overvoltage monitor diagnostic. DVDD_OV_EN must be set for the diagnostic to work. The DVDD_OVn fault flag sets within tp(DVDD_OV) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
10DVDD_UV_DIAG_ENR/W0bDVDD LDO undervoltage monitor diagnostic enable
Enables the DVDD LDO output undervoltage monitor diagnostic. DVDD_UV_EN must be set for the diagnostic to work. The DVDD_UVn fault flag sets within tp(DVDD_UV) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
9AVDD_OSC_DIAG_ENR/W0bAVDD LDO oscillation monitor diagnostic enable
Enables the AVDD LDO output oscillation monitor diagnostic. AVDD_OSC_EN must be set for the diagnostic to work. The AVDD_OSCn fault flag sets within tp(AVDD_OSC) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
8IOVDD_OSC_DIAG_ENR/W0bIOVDD LDO oscillation monitor diagnostic enable
Enables the IOVDD LDO output oscillation monitor diagnostic. IOVDD_OSC_EN must be set for the diagnostic to work. The IOVDD_OSCn fault flag sets within tp(IOVDD_OSC) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
7DVDD_OSC_DIAG_ENR/W0bDVDD LDO oscillation monitor diagnostic enable
Enables the DVDD LDO output oscillation monitor diagnostic. DVDD_OSC_EN must be set for the diagnostic to work. The DVDD_OSCn fault flag sets within tp(DVDD_OSC) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
6:3RESERVEDR0000bReserved
Always reads back 0000b.
2AGNDA_DISC_DIAG_ENR/W0bAGNDA disconnect monitor diagnostic enable
Enables the AGNDA disconnect monitor diagnostic. AGNDA_DISC_EN must be set for the diagnostic to work. The AGNDA_DISCn fault flag sets within tp(AGNDA_OPEN) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
1AGNDB_DISC_DIAG_ENR/W0bAGNDB disconnect monitor diagnostic enable
Enables the AGNDB disconnect monitor diagnostic. AGNDB_DISC_EN must be set for the diagnostic to work. The AGNDB_DISCn fault flag sets within tp(AGNDB_OPEN) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
0DGND_DISC_DIAG_ENR/W0bDGND disconnect monitor diagnostic enable
Enables the DGND disconnect monitor diagnostic. DGND_DISC_EN must be set for the diagnostic to work. The DGND_DISCn fault flag sets within tp(DGND_OPEN) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled

8.6.1.32 CLOCK_MONITOR_DIAGNOSTIC_CFG Register (Address = 45h) [Reset = 0000h]

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Figure 8-77 CLOCK_MONITOR_DIAGNOSTIC_CFG Register
15141312111098
SPARE[11:0]
R/W-000000000000b
76543210
SPARE[11:0]MCLK_HI_DIAG_ENMCLK_LO_DIAG_ENOSCD_WD_DIAG_ENMCLK_WD_DIAG_EN
R/W-000000000000bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-57 CLOCK_MONITOR_DIAGNOSTIC_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:4SPARE[11:0]R/W000000000000bSpare bits
Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings have no effect.
3MCLK_HI_DIAG_ENR/W0bMCLK frequency too high monitor diagnostic enable
Enables the main clock frequency too high monitor diagnostic. MCLK_MON_EN must be set for the diagnostic to work. The MCLK_FAULTn fault flag sets within tp(MCLK_FAULT) when the diagnostic completed successfully. Do not enable the MCLK_LO_DIAG_EN at the same time. Execute the MCLK_HI_DIAG_EN and MCLK_LO_DIAG_EN sequentially.
0b = Disabled
1b = Enabled
2MCLK_LO_DIAG_ENR/W0bMCLK frequency too low monitor diagnostic enable
Enables the main clock frequency too low monitor diagnostic. MCLK_MON_EN must be set for the diagnostic to work. The MCLK_FAULTn fault flag sets within tp(MCLK_FAULT) when the diagnostic completed successfully. Do not enable the MCLK_HI_DIAG_EN at the same time. Execute the MCLK_HI_DIAG_EN and MCLK_LO_DIAG_EN sequentially.
0b = Disabled
1b = Enabled
1OSCD_WD_DIAG_ENR/W0bDiagnostic oscillator watchdog diagnostic enable
Enables the diagnostic oscillator watchdog diagnostic. OSCD_WD_EN must be set for the diagnostic to work. The OSCD_WDn fault flag sets within tp(OSCD_WD) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled
0MCLK_WD_DIAG_ENR/W0bMain clock watchdog diagnostic enable
Enables the main clock watchdog diagnostic. MCLK_WD_EN must be set for the diagnostic to work. The MCLK_WDn fault flag sets within tp(MCLK_WD) when the diagnostic completed successfully.
0b = Disabled
1b = Enabled

8.6.1.33 DIGITAL_MONITOR_DIAGNOSTIC_CFG Register (Address = 46h) [Reset = 0000h]

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Figure 8-78 DIGITAL_MONITOR_DIAGNOSTIC_CFG Register
15141312111098
RESERVEDMEM_MAP_CRC_DIAG[1:0]
R-000000bR/W-00b
76543210
RESERVEDGPIOA_DIAG_ENGPIOB_DIAG_ENGPIO_DIAG_EN
R-00000bR/W-0bR/W-0bR/W-0b
Table 8-58 DIGITAL_MONITOR_DIAGNOSTIC_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR000000bReserved
Always reads back 000000b.
9:8MEM_MAP_CRC_DIAG[1:0]R/W00bMemory map CRC diagnostic bit pattern selection
Selects the bit pattern to use for the memory map CRC diagnostic. The MEM_MAP_CRC_FAULTn fault flag sets within tp(MEM_MAP_CRC) when the diagnostic completed successfully. Any of the three available bit patterns can be used for the diagnostic.
00b = Disabled
01b = Pattern 1
10b = Pattern 2
11b = Pattern 3
7:3RESERVEDR00000bReserved
Always reads back 00000b.
2GPIOA_DIAG_ENR/W0bGPIOA readback diagnostic enable
Inverts the readback value of the GPIxA_DAT[1:0] bits if GPIOxA_DIR is configured as a digital output.
0b = Disabled
1b = Enabled
1GPIOB_DIAG_ENR/W0bGPIOB readback diagnostic enable
Inverts the readback value of the GPIxB_DAT[1:0] bits if GPIOxB_DIR is configured as a digital output.
0b = Disabled
1b = Enabled
0GPIO_DIAG_ENR/W0bGPIO readback diagnostic enable
Inverts the readback value of the GPIx_DAT[1:0] bits if GPIOx_DIR is configured as a digital output.
0b = Disabled
1b = Enabled

8.6.1.34 SUPPLY_FAULT_MASK Register (Address = 47h) [Reset = 0000h]

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Figure 8-79 SUPPLY_FAULT_MASK Register
15141312111098
AVDD_OV_MASKAVDD_UV_MASKIOVDD_OV_MASKIOVDD_UV_MASKDVDD_OV_MASKDVDD_UV_MASKAVDD_OSC_MASKIOVDD_OSC_MASK
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
76543210
DVDD_OSC_MASKAVDD_OTW_MASKIOVDD_OTW_MASKAVDD_CL_MASKIOVDD_CL_MASKAGNDA_DISC_MASKAGNDB_DISC_MASKDGND_DISC_MASK
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-59 SUPPLY_FAULT_MASK Register Field Descriptions
BitFieldTypeResetDescription
15AVDD_OV_MASKR/W0bAVDD overvoltage fault flag mask
Masks the AVDD overvoltage fault flag (AVDD_OVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
14AVDD_UV_MASKR/W0bAVDD undervoltage fault flag mask
Masks the AVDD undervoltage fault flag (AVDD_UVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
13IOVDD_OV_MASKR/W0bIOVDD overvoltage fault flag mask
Masks the IOVDD overvoltage fault flag (IOVDD_OVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
12IOVDD_UV_MASKR/W0bIOVDD undervoltage fault flag mask
Masks the IOVDD undervoltage fault flag (IOVDD_UVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
11DVDD_OV_MASKR/W0bDVDD overvoltage fault flag mask
Masks the DVDD overvoltage fault flag (DVDD_OVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
10DVDD_UV_MASKR/W0bDVDD undervoltage fault flag mask
Masks the DVDD undervoltage fault flag (DVDD_UVn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
9AVDD_OSC_MASKR/W0bAVDD oscillation fault flag mask
Masks the AVDD oscillation fault flag (AVDD_OSCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
8IOVDD_OSC_MASKR/W0bIOVDD oscillation fault flag mask
Masks the IOVDD oscillation fault flag (IOVDD_OSCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
7DVDD_OSC_MASKR/W0bDVDD oscillation fault flag mask
Masks the DVDD oscillation fault flag (DVDD_OSCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
6AVDD_OTW_MASKR/W0bAVDD overtemperature warning flag mask
Masks the AVDD LDO overtemperature warning flag (AVDD_OTWn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
5IOVDD_OTW_MASKR/W0bIOVDD overtemperature warning flag mask
Masks the IOVDD LDO overtemperature warning flag (IOVDD_OTWn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
4AVDD_CL_MASKR/W0bAVDD current limit flag mask
Masks the AVDD LDO current limit flag (AVDD_CLn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
3IOVDD_CL_MASKR/W0bIOVDD current limit flag mask
Masks the IOVDD LDO current limit flag (IOVDD_CLn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
2AGNDA_DISC_MASKR/W0bAGNDA pin disconnect detection flag mask
Masks the AGNDA pin disconnect detection flag (AGNDA_DISCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
1AGNDB_DISC_MASKR/W0bAGNDB pin disconnect detection flag mask
Masks the AGNDB pin disconnect detection flag (AGNDB_DISCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
0DGND_DISC_MASKR/W0bDGND pin disconnect detection flag mask
Masks the DGND pin disconnect detection flag (DGND_DISCn) from triggering the SUPPLY_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked

8.6.1.35 CLOCK_FAULT_MASK Register (Address = 48h) [Reset = 0000h]

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Figure 8-80 CLOCK_FAULT_MASK Register
15141312111098
RESERVEDRESERVED
R/W-000000bR-0000000b
76543210
RESERVEDMCLK_FAULT_MASKOSCD_WD_MASKMCLK_WD_MASK
R-0000000bR/W-0bR/W-0bR/W-0b
Table 8-60 CLOCK_FAULT_MASK Register Field Descriptions
BitFieldTypeResetDescription
15:10RESERVEDR/W000000bReserved
Always write 000000b.
9:3RESERVEDR0000000bReserved
Always reads back 0000000b.
2MCLK_FAULT_MASKR/W0bMCLK frequency too high or too low fault flag mask
Masks the MCLK frequency too high or too low fault flag (MCLK_FAULTn) from triggering the CLOCK_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
1OSCD_WD_MASKR/W0bDiagnostic oscillator watchdog fault flag mask
Masks the diagnostic oscillator watchdog fault flag (OSCD_WDn) from triggering the CLOCK_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
0MCLK_WD_MASKR/W0bMain clock watchdog fault flag mask
Masks the main clock watchdog fault flag (MCLK_WDn) from triggering the CLOCK_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked

8.6.1.36 DIGITAL_FAULT_MASK Register (Address = 49h) [Reset = 0000h]

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Figure 8-81 DIGITAL_FAULT_MASK Register
15141312111098
REG_MAP1_CRC_FAULT_MASKREG_MAP2_CRC_FAULT_MASKREG_MAP3_CRC_FAULT_MASKRESERVEDMEM_MAP_CRC_FAULT_MASKRESERVED
R/W-0bR/W-0bR/W-0bR-0bR/W-0bR-00000000000b
76543210
RESERVED
R-00000000000b
Table 8-61 DIGITAL_FAULT_MASK Register Field Descriptions
BitFieldTypeResetDescription
15REG_MAP1_CRC_FAULT_MASKR/W0bRegister map section 1 CRC fault flag mask
Masks the register map section 1 CRC fault flag (REG_MAP1_CRC_FAULTn) from triggering the DIGITAL_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
14REG_MAP2_CRC_FAULT_MASKR/W0bRegister map section 2 CRC fault flag mask
Masks the register map section 2 CRC fault flag (REG_MAP2_CRC_FAULTn) from triggering the DIGITAL_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
13REG_MAP3_CRC_FAULT_MASKR/W0bRegister map section 3 CRC fault flag mask
Masks the register map section 3 CRC fault flag (REG_MAP3_CRC_FAULTn) from triggering the DIGITAL_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
12RESERVEDR0bReserved
Always reads back 0b.
11MEM_MAP_CRC_FAULT_MASKR/W0bMemory map CRC fault flag mask
Masks the memory map CRC fault flag (MEM_MAP_CRC_FAULTn) from triggering the DIGITAL_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
10:0RESERVEDR00000000000bReserved
Always reads back 00000000000b.

8.6.1.37 OCC_FAULT_MASK Register (Address = 4Ah) [Reset = 0000h]

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Figure 8-82 OCC_FAULT_MASK Register
15141312111098
RESERVED
R-000000000000b
76543210
RESERVEDOCCA_HT_MASKOCCA_LT_MASKOCCB_HT_MASKOCCB_LT_MASK
R-000000000000bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-62 OCC_FAULT_MASK Register Field Descriptions
BitFieldTypeResetDescription
15:4RESERVEDR000000000000bReserved
Always reads back 000000000000b.
3OCCA_HT_MASKR/W0bADC1A overcurrent comparator high threshold fault flag mask
Masks the ADC1A overcurrent comparator high threshold fault flag (OCCA_HTn) from triggering the OCC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
2OCCA_LT_MASKR/W0bADC1A overcurrent comparator low threshold fault flag mask
Masks the ADC1A overcurrent comparator low threshold fault flag (OCCA_LTn) from triggering the OCC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
1OCCB_HT_MASKR/W0bADC1B overcurrent comparator high threshold fault flag mask
Masks the ADC1B overcurrent comparator high threshold fault flag (OCCB_HTn) from triggering the OCC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked
0OCCB_LT_MASKR/W0bADC1B overcurrent comparator low threshold fault flag mask
Masks the ADC1B overcurrent comparator low threshold fault flag (OCCB_LTn) from triggering the OCC_FAULTn flag in the STATUS_MSB register.
0b = Unmasked
1b = Masked

8.6.1.38 FAULT_PIN_MASK Register (Address = 4Bh) [Reset = 0780h]

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Figure 8-83 FAULT_PIN_MASK Register
15141312111098
RESERVEDSUPPLY_FAULT_MASKCLOCK_FAULT_MASKDIGITAL_FAULT_MASKOCC_FAULT_MASKSPI_CRC_FAULT_MASKSPI_TIMEOUT_MASKSCLK_COUNT_FAULT_MASK
R-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-1bR/W-1bR/W-1b
76543210
REG_ACCESS_FAULT_MASKRESERVED
R/W-1bR-0000000b
Table 8-63 FAULT_PIN_MASK Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0bReserved
Always reads back 0b.
14SUPPLY_FAULT_MASKR/W0bSupply fault flag mask
Masks the supply fault flag (SUPPLY_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
13CLOCK_FAULT_MASKR/W0bClock fault flag mask
Masks the clock fault flag (CLOCK_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
12DIGITAL_FAULT_MASKR/W0bDigital fault flag mask
Masks the digital fault flag (DIGITAL_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
11OCC_FAULT_MASKR/W0bOvercurrent comparator fault flag mask
Masks the overcurrent comparator fault flag (OCC_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
10SPI_CRC_FAULT_MASKR/W1bSPI CRC fault flag mask
Masks the SPI CRC fault flag (SPI_CRC_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
9SPI_TIMEOUT_MASKR/W1bSPI timeout fault flag mask
Masks the SPI timeout fault flag (SPI_TIMEOUTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
8SCLK_COUNT_FAULT_MASKR/W1bSCLK counter fault flag mask
Masks the SCLK counter fault flag (SCLK_COUNT_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
7REG_ACCESS_FAULT_MASKR/W1bRegister access fault flag mask
Masks the register access fault flag (REG_ACCESS_FAULTn) in the STATUS_MSB register from triggering the FAULT pin when the GPIO2/FAULT pin is configured as a FAULT output.
0b = Unmasked
1b = Masked
6:0RESERVEDR0000000bReserved
Always reads back 00000000b.

8.6.1.39 DEVICE_CFG Register (Address = 4Ch) [Reset = 0000h]

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Figure 8-84 DEVICE_CFG Register
15141312111098
RESERVEDDRDY_CTRLRESERVEDCLK_SOURCEWORD_LENGTHRESERVEDOP_MODE[1:0]
R-0bR/W-0bR/W-0bR/W-0bR/W-0bR-0bR/W-00b
76543210
RESERVED
R-00000000b
Table 8-64 DEVICE_CFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0bReserved
Always reads back 0b.
14DRDY_CTRLR/W0bDRDYn pin control selection
Selects which ADC controls the DRDYn pin indication.
0b = ADC1A
1b = ADC1B
13RESERVEDR/W0bReserved
Always write 0b.
12CLK_SOURCER/W0bMCLK clock source selection
Selects the main clock source of the device. Before changing this bit, all ADCs must be disabled or the device placed in standby or power-down mode. When switching from an external clock to the internal oscillator, the external clock must be provided until after the switch-over is complete.
0b = Internal oscillator
1b = External clock
11WORD_LENGTHR/W0bData word length selection
Selects the length of every word in the SPI frame.
0b = 24 bits
1b = 32 bits; LSB zero padding
10RESERVEDR0bReserved
Always reads back 0b.
9:8OP_MODE[1:0]R/W00bOperating mode selection
Selects the operating mode for the device.
00b = Active mode
01b = Standby mode (Disables all ADCs)
10b = Power-down mode
11b = Power-down mode
7:0RESERVEDR00000000bReserved
Always reads back 00000000b.

8.6.1.40 GPIO_CFG Register (Address = 4Dh) [Reset = 0000h]

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Figure 8-85 GPIO_CFG Register
15141312111098
RESERVEDGPIO4_FMTGPIO3_FMTGPIO2_FMTGPIO1_FMTGPIO0_FMTGPIO4_DIRGPIO3_DIR
R-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
76543210
GPIO2_DIRGPIO1_DIRGPIO0_DIRGPIO4_SRCGPIO3_SRCGPIO2_SRCRESERVEDGPIO0_SRC
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR-0bR/W-0b
Table 8-65 GPIO_CFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0bReserved
Always reads back 0b.
14GPIO4_FMTR/W0bGPIO4 format
Configures GPIO4 for static input and output levels or for PWM input and output levels
0b = When GPIO4 is configured as a digital input: Logic levels are based on static input levels. When GPIO4 is configured as a digital output: Output with static output levels. (GPIO4_LL_PWM_CFG and GPIO4_LH_PWM_CFG registers are ignored in this case). For parallel GPO readback purposes the readback path is configured for logic levels based on static input levels in this case.
1b = When GPIO4 is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO4 is configured as a digital output: Output with PWM output defined by the GPIO4_LL_PWM_CFG and GPIO4_LH_PWM_CFG registers. For parallel GPO readback purposes the readback path is configured for logic levels based on PWM decoding using the time base configured in GPIO4_PWM_TB in this case.
13GPIO3_FMTR/W0bGPIO3 format
Configures GPIO3 for static input and output levels or for PWM input and output levels
0b = When GPIO3 is configured as a digital input: Logic levels are based on static input levels. When GPIO3 is configured as a digital output: Output with static output levels. (GPIO3_LL_PWM_CFG and GPIO3_LH_PWM_CFG registers are ignored in this case). For parallel GPO readback purposes the readback path is configured for logic levels based on static input levels in this case.
1b = When GPIO3 is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO3 is configured as a digital output: Output with PWM output defined by the GPIO3_LL_PWM_CFG and GPIO3_LH_PWM_CFG registers. For parallel GPO readback purposes the readback path is configured for logic levels based on PWM decoding using the time base configured in GPIO3_PWM_TB in this case.
12GPIO2_FMTR/W0bGPIO2 format
Configures GPIO2 for static input and output levels or for PWM input and output levels
0b = When GPIO2 is configured as a digital input: Logic levels are based on static input levels. When GPIO2 is configured as a digital output: Output with static output levels. (GPIO2_LL_PWM_CFG and GPIO2_LH_PWM_CFG registers are ignored in this case). For parallel GPO readback purposes the readback path is configured for logic levels based on static input levels in this case.
1b = When GPIO2 is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO2 is configured as a digital output: Output with PWM output defined by the GPIO2_LL_PWM_CFG and GPIO2_LH_PWM_CFG registers. For parallel GPO readback purposes the readback path is configured for logic levels based on PWM decoding using the time base configured in GPIO2_PWM_TB in this case.
11GPIO1_FMTR/W0bGPIO1 format
Configures GPIO1 for static input and output levels or for PWM input and output levels
0b = When GPIO1 is configured as a digital input: Logic levels are based on static input levels. When GPIO1 is configured as a digital output: Output with static output levels. (GPIO1_LL_PWM_CFG and GPIO1_LH_PWM_CFG registers are ignored in this case). For parallel GPO readback purposes the readback path is configured for logic levels based on static input levels in this case.
1b = When GPIO1 is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO1 is configured as a digital output: Output with PWM output defined by the GPIO1_LL_PWM_CFG and GPIO1_LH_PWM_CFG registers. For parallel GPO readback purposes the readback path is configured for logic levels based on PWM decoding using the time base configured in GPIO1_PWM_TB in this case.
10GPIO0_FMTR/W0bGPIO0 format
Configures GPIO0 for static input and output levels or for PWM input and output levels
0b = When GPIO0 is configured as a digital input: Logic levels are based on static input levels. When GPIO0 is configured as a digital output: Output with static output levels. (GPIO0_LL_PWM_CFG and GPIO0_LH_PWM_CFG registers are ignored in this case). For parallel GPO readback purposes the readback path is configured for logic levels based on static input levels in this case.
1b = When GPIO0 is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO0 is configured as a digital output: Output with PWM output defined by the GPIO0_LL_PWM_CFG and GPIO0_LH_PWM_CFG registers. For parallel GPO readback purposes the readback path is configured for logic levels based on PWM decoding using the time base configured in GPIO0_PWM_TB in this case.
9GPIO4_DIRR/W0bGPIO4 direction
Configures GPIO4 as a digital input or output. Configure as a digital output when used as OCCB output.
0b = Digital input
1b = Digital output
8GPIO3_DIRR/W0bGPIO3 direction
Configures GPIO3 as a digital input or output. Configure as a digital output when used as OCCA output.
0b = Digital input
1b = Digital output
7GPIO2_DIRR/W0bGPIO2 direction
Configures GPIO2 as a digital input or output. Configure as a digital output when used as FAULT output.
0b = Digital input
1b = Digital output
6GPIO1_DIRR/W0bGPIO1 direction
Configures GPIO1 as a digital input or output.
0b = Digital input
1b = Digital output
5GPIO0_DIRR/W0bGPIO0 direction
Configures GPIO0 as a digital input or output. Configure as a digital output when used as MHD output.
0b = Digital input
1b = Digital output
4GPIO4_SRCR/W0bGPIO4 data source selection
Selects the data source of the GPIO4/OCCB pin when GPIO4 is configured as an output.
0b = OCCB
1b = GPIO
3GPIO3_SRCR/W0bGPIO3 data source selection
Selects the data source of the GPIO3/OCCA pin when GPIO3 is configured as an output.
0b = OCCA
1b = GPIO
2GPIO2_SRCR/W0bGPIO2 data source selection
Selects the data source of the GPIO2/FAULT pin when GPIO2 is configured as an output.
0b = FAULT
1b = GPIO
1RESERVEDR0bReserved
Always reads back 0b.
0GPIO0_SRCR/W0bGPIO0 data source selection
Selects the data source of the GPIO0/MHD pin when GPIO0 is configured as an output.
0b = Missing host detection (MHD)
1b = GPIO

8.6.1.41 GPO_DATA Register (Address = 4Eh) [Reset = 0000h]

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Figure 8-86 GPO_DATA Register
15141312111098
SPARE[10:0]
R/W-00000000000b
76543210
SPARE[10:0]GPO4_DATGPO3_DATGPO2_DATGPO1_DATGPO0_DAT
R/W-00000000000bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 8-66 GPO_DATA Register Field Descriptions
BitFieldTypeResetDescription
15:5SPARE[10:0]R/W00000000000bSpare bits
Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings have no effect.
4GPO4_DATR/W0bGPIO4 output data
Output value of GPIO4 when configured as a digital output. Bit setting has not effect when GPIO4 is configured as an input or as OCCB output.
0b = Low
1b = High
3GPO3_DATR/W0bGPIO3 output data
Output value of GPIO3 when configured as a digital output. Bit setting has not effect when GPIO3 is configured as an input or as OCCA output.
0b = Low
1b = High
2GPO2_DATR/W0bGPIO2 output data
Output value of GPIO2 when configured as a digital output. Bit setting has not effect when GPIO2 is configured as an input or as FAULT output.
0b = Low
1b = High
1GPO1_DATR/W0bGPIO1 output data
Output value of GPIO1 when configured as a digital output. Bit setting has not effect when GPIO1 is configured as an input.
0b = Low
1b = High
0GPO0_DATR/W0bGPIO0 output data
Output value of GPIO0 when configured as a digital output. Bit setting has not effect when GPIO0 is configured as an input or as MHD output.
0b = Low
1b = High

8.6.1.42 GPIO0_LL_PWM_CFG Register (Address = 4Fh) [Reset = 007Fh]

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Figure 8-87 GPIO0_LL_PWM_CFG Register
15141312111098
GPIO0_PWM_TB[1:0]GPIO0_LL_PWM_HC[6:0]
R/W-00bR/W-0000000b
76543210
GPIO0_LL_PWM_HC[6:0]GPIO0_LL_PWM_LC[6:0]
R/W-0000000bR/W-1111111b
Table 8-67 GPIO0_LL_PWM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:14GPIO0_PWM_TB[1:0]R/W00bGPIO0/MHD PWM time base selection
Selects the time base used for the GPIO0/MHD PWM generation when the GPIO0/MHD pin is configured as an output as well as the time base used for the PWM encoder.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
13:7GPIO0_LL_PWM_HC[6:0]R/W0000000bGPIO0/MHD logic low level PWM high counter
Sets the high period of the PWM for a logic low level of GPIO0/MHD.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO0/MHD logic low level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO0/MHD logic low level as static low.
6:0GPIO0_LL_PWM_LC[6:0]R/W1111111bGPIO0/MHD logic low level PWM low counter
Sets the low period of the PWM for a logic low level of GPIO0/MHD.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO0/MHD logic low level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO0/MHD logic low level as static low.

8.6.1.43 GPIO0_LH_PWM_CFG Register (Address = 50h) [Reset = 3F80h]

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Figure 8-88 GPIO0_LH_PWM_CFG Register
15141312111098
RESERVEDGPIO0_LH_PWM_HC[6:0]
R-00bR/W-1111111b
76543210
GPIO0_LH_PWM_HC[6:0]GPIO0_LH_PWM_LC[6:0]
R/W-1111111bR/W-0000000b
Table 8-68 GPIO0_LH_PWM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR00bReserved
Always reads 00b.
13:7GPIO0_LH_PWM_HC[6:0]R/W1111111bGPIO0/MHD logic high level PWM high counter
Sets the high period of the PWM for a logic high level of GPIO0/MHD.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO0/MHD logic high level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO0/MHD logic high level as static low.
6:0GPIO0_LH_PWM_LC[6:0]R/W0000000bGPIO0/MHD logic high level PWM low counter
Sets the low period of the PWM for a logic high level of GPIO0/MHD.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO0/MHD logic high level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO0/MHD logic high level as static low.

8.6.1.44 GPIO1_LL_PWM_CFG Register (Address = 51h) [Reset = 007Fh]

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Figure 8-89 GPIO1_LL_PWM_CFG Register
15141312111098
GPIO1_PWM_TB[1:0]GPIO1_LL_PWM_HC[6:0]
R/W-00bR/W-0000000b
76543210
GPIO1_LL_PWM_HC[6:0]GPIO1_LL_PWM_LC[6:0]
R/W-0000000bR/W-1111111b
Table 8-69 GPIO1_LL_PWM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:14GPIO1_PWM_TB[1:0]R/W00bGPIO1 PWM time base selection
Selects the time base used for the GPIO1 PWM generation when the GPIO1 pin is configured as an output as well as the time base used for the PWM encoder.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
13:7GPIO1_LL_PWM_HC[6:0]R/W0000000bGPIO1 logic low level PWM high counter
Sets the high period of the PWM for a logic low level of GPIO1.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO1 logic low level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO1 logic low level as static low.
6:0GPIO1_LL_PWM_LC[6:0]R/W1111111bGPIO1 logic low level PWM low counter
Sets the low period of the PWM for a logic low level of GPIO1.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO1 logic low level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO1 logic low level as static low.

8.6.1.45 GPIO1_LH_PWM_CFG Register (Address = 52h) [Reset = 3F80h]

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Figure 8-90 GPIO1_LH_PWM_CFG Register
15141312111098
RESERVEDGPIO1_LH_PWM_HC[6:0]
R-00bR/W-1111111b
76543210
GPIO1_LH_PWM_HC[6:0]GPIO1_LH_PWM_LC[6:0]
R/W-1111111bR/W-0000000b
Table 8-70 GPIO1_LH_PWM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR00bReserved
Always reads 00b.
13:7GPIO1_LH_PWM_HC[6:0]R/W1111111bGPIO1 logic high level PWM high counter
Sets the high period of the PWM for a logic high level of GPIO1.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO1 logic high level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO1 logic high level as static low.
6:0GPIO1_LH_PWM_LC[6:0]R/W0000000bGPIO1 logic high level PWM low counter
Sets the low period of the PWM for a logic high level of GPIO1.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO1 logic high level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO1 logic high level as static low.

8.6.1.46 GPIO2_LL_PWM_CFG Register (Address = 53h) [Reset = 007Fh]

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Figure 8-91 GPIO2_LL_PWM_CFG Register
15141312111098
GPIO2_PWM_TB[1:0]GPIO2_LL_PWM_HC[6:0]
R/W-00bR/W-0000000b
76543210
GPIO2_LL_PWM_HC[6:0]GPIO2_LL_PWM_LC[6:0]
R/W-0000000bR/W-1111111b
Table 8-71 GPIO2_LL_PWM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:14GPIO2_PWM_TB[1:0]R/W00bGPIO2/FAULT PWM time base selection
Selects the time base used for the GPIO2/FAULT PWM generation when the GPIO2/FAULT pin is configured as an output as well as the time base used for the PWM encoder.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
13:7GPIO2_LL_PWM_HC[6:0]R/W0000000bGPIO2/FAULT logic low level PWM high counter
Sets the high period of the PWM for a logic low level of GPIO2/FAULT.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO2/FAULT logic low level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/FAULT logic low level as static low.
6:0GPIO2_LL_PWM_LC[6:0]R/W1111111bGPIO2/FAULT logic low level PWM low counter
Sets the low period of the PWM for a logic low level of GPIO2/FAULT.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO2/FAULT logic low level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/FAULT logic low level as static low.

8.6.1.47 GPIO2_LH_PWM_CFG Register (Address = 54h) [Reset = 3F80h]

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Figure 8-92 GPIO2_LH_PWM_CFG Register
15141312111098
RESERVEDGPIO2_LH_PWM_HC[6:0]
R-00bR/W-1111111b
76543210
GPIO2_LH_PWM_HC[6:0]GPIO2_LH_PWM_LC[6:0]
R/W-1111111bR/W-0000000b
Table 8-72 GPIO2_LH_PWM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR00bReserved
Always reads 00b.
13:7GPIO2_LH_PWM_HC[6:0]R/W1111111bGPIO2/FAULT logic high level PWM high counter
Sets the high period of the PWM for a logic high level of GPIO2/FAULT.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO2/FAULT logic high level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/FAULT logic high level as static low.
6:0GPIO2_LH_PWM_LC[6:0]R/W0000000bGPIO2/FAULT logic high level PWM low counter
Sets the low period of the PWM for a logic high level of GPIO2/FAULT.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO2/FAULT logic high level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/FAULT logic high level as static low.

8.6.1.48 GPIO3_LL_PWM_CFG Register (Address = 55h) [Reset = 007Fh]

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Figure 8-93 GPIO3_LL_PWM_CFG Register
15141312111098
GPIO3_PWM_TB[1:0]GPIO3_LL_PWM_HC[6:0]
R/W-00bR/W-0000000b
76543210
GPIO3_LL_PWM_HC[6:0]GPIO3_LL_PWM_LC[6:0]
R/W-0000000bR/W-1111111b
Table 8-73 GPIO3_LL_PWM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:14GPIO3_PWM_TB[1:0]R/W00bGPIO3/OCCA PWM time base selection
Selects the time base used for the GPIO3/OCCA PWM generation when the GPIO3/OCCA pin is configured as an output as well as the time base used for the PWM encoder.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
13:7GPIO3_LL_PWM_HC[6:0]R/W0000000bGPIO3/OCCA logic low level PWM high counter
Sets the high period of the PWM for a logic low level of GPIO3/OCCA.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO3/OCCA logic low level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO3/OCCA logic low level as static low.
6:0GPIO3_LL_PWM_LC[6:0]R/W1111111bGPIO3/OCCA logic low level PWM low counter
Sets the low period of the PWM for a logic low level of GPIO3/OCCA.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO3/OCCA logic low level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO3/OCCA logic low level as static low.

8.6.1.49 GPIO3_LH_PWM_CFG Register (Address = 56h) [Reset = 3F80h]

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Figure 8-94 GPIO3_LH_PWM_CFG Register
15141312111098
RESERVEDGPIO3_LH_PWM_HC[6:0]
R-00bR/W-1111111b
76543210
GPIO3_LH_PWM_HC[6:0]GPIO3_LH_PWM_LC[6:0]
R/W-1111111bR/W-0000000b
Table 8-74 GPIO3_LH_PWM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR00bReserved
Always reads 00b.
13:7GPIO3_LH_PWM_HC[6:0]R/W1111111bGPIO3/OCCA logic high level PWM high counter
Sets the high period of the PWM for a logic high level of GPIO3/OCCA.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO3/OCCA logic high level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/OCCA logic high level as static low.
6:0GPIO3_LH_PWM_LC[6:0]R/W0000000bGPIO3/OCCA logic high level PWM low counter
Sets the low period of the PWM for a logic high level of GPIO3/OCCA.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO3/OCCA logic high level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO2/OCCA logic high level as static low.

8.6.1.50 GPIO4_LL_PWM_CFG Register (Address = 57h) [Reset = 007Fh]

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Figure 8-95 GPIO4_LL_PWM_CFG Register
15141312111098
GPIO4_PWM_TB[1:0]GPIO4_LL_PWM_HC[6:0]
R/W-00bR/W-0000000b
76543210
GPIO4_LL_PWM_HC[6:0]GPIO4_LL_PWM_LC[6:0]
R/W-0000000bR/W-1111111b
Table 8-75 GPIO4_LL_PWM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:14GPIO4_PWM_TB[1:0]R/W00bGPIO4/OCCB PWM time base selection
Selects the time base used for the GPIO4/OCCB PWM generation when the GPIO4/OCCB pin is configured as an output as well as the time base used for the PWM encoder
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
13:7GPIO4_LL_PWM_HC[6:0]R/W0000000bGPIO4/OCCB logic low level PWM high counter
Sets the high period of the PWM for a logic low level of GPIO4/OOCB.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO4/OCCB logic low level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO4/OCCB logic low level as static low.
6:0GPIO4_LL_PWM_LC[6:0]R/W1111111bGPIO4/OCCB logic low level PWM low counter
Sets the low period of the PWM for a logic low level of GPIO4/OCCB.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO4/OCCB logic low level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO4/OCCB logic low level as static low.

8.6.1.51 GPIO4_LH_PWM_CFG Register (Address = 58h) [Reset = 3F80h]

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Figure 8-96 GPIO4_LH_PWM_CFG Register
15141312111098
RESERVEDGPIO4_LH_PWM_HC[6:0]
R-00bR/W-1111111b
76543210
GPIO4_LH_PWM_HC[6:0]GPIO4_LH_PWM_LC[6:0]
R/W-1111111bR/W-0000000b
Table 8-76 GPIO4_LH_PWM_CFG Register Field Descriptions
BitFieldTypeResetDescription
15:14RESERVEDR00bReserved
Always reads 00b.
13:7GPIO4_LH_PWM_HC[6:0]R/W1111111bGPIO4BOCCB logic high level PWM high counter
Sets the high period of the PWM for a logic high level of GPIO4.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM high time = (PWM high counter value x PWM time base)
Setting the PWM high counter value to 0000000b configures the GPIO4 logic high level as static low. Setting both the PWM high and low counter values to 0000000b configures the GPIO4/OCCB logic high level as static low.
6:0GPIO4_LH_PWM_LC[6:0]R/W0000000bGPIO4/OCCB logic high level PWM low counter
Sets the low period of the PWM for a logic high level of GPIO4/OCCB.
PWM period = (PWM high counter value + PWM low counter value) x PWM time base
PWM low time = (PWM low counter value x PWM time base)
Setting the PWM low counter value to 0000000b configures the GPIO4/OCCB logic high level as static high. Setting both the PWM high and low counter values to 0000000b configures the GPIO4/OCCB logic high level as static low.

8.6.1.52 SPARE_59h Register (Address = 59h) [Reset = 5555h]

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Figure 8-97 SPARE_59h Register
15141312111098
SPARE[15:0]
R/W-0101010101010101b
76543210
SPARE[15:0]
R/W-0101010101010101b
Table 8-77 SPARE_59h Register Field Descriptions
BitFieldTypeResetDescription
15:0SPARE[15:0]R/W0101010101010101bSpare bits
Provided as R/W bits as a means to check the register map section 1 CRC. Bit settings have no effect.

8.6.1.53 REGISTER_MAP1_CRC Register (Address = 7Eh) [Reset = 0000h]

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Figure 8-98 REGISTER_MAP1_CRC Register
15141312111098
REG_MAP1_CRC_VALUE[15:0]
R/W-0000000000000000b
76543210
REG_MAP1_CRC_VALUE[15:0]
R/W-0000000000000000b
Table 8-78 REGISTER_MAP1_CRC Register Field Descriptions
BitFieldTypeResetDescription
15:0REG_MAP1_CRC_VALUE[15:0]R/W0000000000000000bRegister map CRC value for section 1
Register map CRC value for section 1.

8.6.1.54 REGMAP2_TDACA_CFG Register (Address = 80h) [Reset = 0000h]

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Figure 8-99 REGMAP2_TDACA_CFG Register
15141312111098
REG_MAP2_CRC_ENRESERVED
R/W-0bR-000000000000b
76543210
RESERVEDTDACA_VALUE[2:0]
R-000000000000bR/W-000b
Table 8-79 REGMAP2_TDACA_CFG Register Field Descriptions
BitFieldTypeResetDescription
15REG_MAP2_CRC_ENR/W0bRegister map section 2 CRC enable
Enables the register map CRC for section 2 (register address space from 80h to A3h).
0b = Disabled
1b = Enabled
14:3RESERVEDR000000000000bReserved
Always reads 000000000000b.
2:0TDACA_VALUE[2:0]R/W000bTest DAC A output value
Selects the output value of Test DAC A.
000b = 1 x VREFA/40
001b = 2 x VREFA/40
010b = 4 x VREFA/40
011b = 9 x VREFA/40
100b = 18 x VREFA/40
101b = 36 x VREFA/40
110b = –4 x VREFA/40
111b = –9 x VREFA/40

8.6.1.55 GPIOA_CFG Register (Address = 81h) [Reset = 8000h]

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Figure 8-100 GPIOA_CFG Register
15141312111098
RESERVEDSPARE[2:0]GPIO1A_FMTGPIO0A_FMTGPIO1A_DIRGPIO0A_DIR
R-1bR/W-000bR/W-0bR/W-0bR/W-0bR/W-0b
76543210
GPIO1A_PWM_TB[1:0]GPIO0A_PWM_TB[1:0]SPARE[1:0]GPO1A_DATGPO0A_DAT
R/W-00bR/W-00bR/W-00bR/W-0bR/W-0b
Table 8-80 GPIOA_CFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR1bReserved
Always reads 1b.
14:12SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.
11GPIO1A_FMTR/W0bGPIO1A format
Configures GPIO1A for static input and output levels or for PWM input levels.
0b = When GPIO1A is configured as a digital input: Logic levels are based on static input levels. When GPIO1A is configured as a digital output: Output with static output levels.
1b = When GPIO1A is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO1A is configured as a digital output: Output with static output levels. GPIO1A does not have PWM output capability.
10GPIO0A_FMTR/W0bGPIO0A format
Configures GPIO0A for static input and output levels or for PWM input levels.
0b = When GPIO0A is configured as a digital input: Logic levels are based on static input levels. When GPIO0A is configured as a digital output: Output with static output levels.
1b = When GPIO0A is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO0A is configured as a digital output: Output with static output levels. GPIO0A does not have PWM output capability.
9GPIO1A_DIRR/W0bGPIO1A direction
Configures GPIO1A as a digital input or digital output.
0b = Digital input
1b = Digital output
8GPIO0A_DIRR/W0bGPIO0A direction
Configures GPIO0A as a digital input or digital output.
0b = Digital input
1b = Digital output
7:6GPIO1A_PWM_TB[1:0]R/W00bGPIO1A PWM time base selection
Selects the time base used for the PWM encoder when GPIO1A is configured as a digital input.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
5:4GPIO0A_PWM_TB[1:0]R/W00bGPIO0A PWM time base selection
Selects the time base used for the PWM encoder when GPIO0A is configured as a digital input.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
3:2SPARE[1:0]R/W00bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.
1GPO1A_DATR/W0bGPIO1A output data
Output value of GPIO1A when configured as a digital output. Bit setting has not effect when GPIO1A is configured as a digital input.
0b = Low
1b = High
0GPO0A_DATR/W0bGPIO0A output data
Output value of GPIO0A when configured as a digital output. Bit setting has not effect when GPIO0A is configured as a digital input.
0b = Low
1b = High

8.6.1.56 ADC1A_CFG1 Register (Address = 82h) [Reset = 0400h]

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Figure 8-101 ADC1A_CFG1 Register
15141312111098
RESERVEDCONV_MODE1AOSR1A[2:0]
R-0000bR/W-0bR/W-100b
76543210
RESERVEDGC1A_ENGC1A_DELAY[2:0]
R-0000bR/W-0bR/W-000b
Table 8-81 ADC1A_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0000bReserved
Always reads 0000b.
11CONV_MODE1AR/W0bConversion mode selection
Selects the conversion mode for ADC1A.
0b = Continuous-conversion mode
1b = Single-shot conversion mode
10:8OSR1A[2:0]R/W100bOversampling ratio selection
Selects the oversampling ratio for ADC1A. The data rate calculates to fMOD / OSR.
000b = 64
001b = 128
010b = 256
011b = 512
100b = 1024
101b = 2048
110b = 4096
111b = 8192
7:4RESERVEDR0000bReserved
Always reads 0000b.
3GC1A_ENR/W0bGlobal-chop mode enable
Enables the global-chop mode for ADC1A.
0b = Disabled
1b = Enabled
2:0GC1A_DELAY[2:0]R/W000bGlobal-chop mode delay time selection
Selects the delay time in global-chop mode for ADC1A.
000b = 2 x tMOD
001b = 4 x tMOD
010b = 8 x tMOD
011b = 16 x tMOD
100b = 32 x tMOD
101b = 64 x tMOD
110b = 128 x tMOD
111b = 256 x tMOD

8.6.1.57 ADC1A_CFG2 Register (Address = 83h) [Reset = 8010h]

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Figure 8-102 ADC1A_CFG2 Register
15141312111098
ADC1A_ENRESERVEDGAIN1A[1:0]MUX1A[1:0]
R/W-1bR-000bR/W-00bR/W-00b
76543210
RESERVEDOWD1A_SOURCE_MUXOWD1A_SINK_MUXOWD1A_SOURCE_VALUE[1:0]OWD1A_SINK_VALUE[1:0]
R-00bR/W-0bR/W-1bR/W-00bR/W-00b
Table 8-82 ADC1A_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15ADC1A_ENR/W1bADC1A enable
Enables ADC1A.
The conversion data of ADC1A reset to 000000h and the conversion counter CONV1A_COUNT[1:0] resets to 00b when ADC1A is disabled or when the device is put in standby or power-down mode.
0b = Disabled
1b = Enabled
14:12RESERVEDR000bReserved
Always reads 000b.
11:10GAIN1A[1:0]R/W00bADC1A gain selection
Selects the gain (FSR = full scale range) of ADC1A. Gains 16 and 32 are digital gains using analog gain = 8.
00b = 4
01b = 8
10b = 16
11b = 32
9:8MUX1A[1:0]R/W00bADC1A multiplexer channel selection
Selects the multiplexer channel for ADC1A.
00b = AINp = CPA, AINn = CNA
01b = AINp = CNA, AINn = CPA
10b = Internal short to AGNDA. Analog inputs CPA, CNA disconnected from ADC1A.
11b = Test DAC B output
7:6RESERVEDR00bReserved
Always reads 00b.
5OWD1A_SOURCE_MUXR/W0bADC1A current source multiplexer selection
Selects the multiplexer channel for the ADC1A current source.
0b = CPA
1b = CNA
4OWD1A_SINK_MUXR/W1bADC1A current sink multiplexer selection
Selects the multiplexer channel for the ADC1A current sink.
0b = CPA
1b = CNA
3:2OWD1A_SOURCE_VALUE[1:0]R/W00bADC1A current source value selection
Selects the current value for the ADC1A current source.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA
1:0OWD1A_SINK_VALUE[1:0]R/W00bADC1A current sink value selection
Selects the current value for the ADC1A current sink.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA

8.6.1.58 ADC1A_OCAL_MSB Register (Address = 84h) [Reset = 0000h]

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Figure 8-103 ADC1A_OCAL_MSB Register
15141312111098
OCAL1A[23:8]
R/W-0000000000000000b
76543210
OCAL1A[23:8]
R/W-0000000000000000b
Table 8-83 ADC1A_OCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0OCAL1A[23:8]R/W0000000000000000bADC1A offset calibration bits [23:8]
Value provided in two's complement format.
LSB size = (2 x VREFA) / (GAIN1A x 224)

8.6.1.59 ADC1A_OCAL_LSB Register (Address = 85h) [Reset = 0000h]

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Figure 8-104 ADC1A_OCAL_LSB Register
15141312111098
OCAL1A[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-84 ADC1A_OCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8OCAL1A[7:0]R/W00000000bADC1A offset calibration bits [7:0]
Value provided in two's complement format.
LSB size = (2 x VREFA) / (GAIN1A x 224)
7:0RESERVEDR00000000bReserved
Always reads 00000000b.

8.6.1.60 ADC1A_GCAL Register (Address = 86h) [Reset = 0000h]

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Figure 8-105 ADC1A_GCAL Register
15141312111098
GCAL1A[15:0]
R/W-0000000000000000b
76543210
GCAL1A[15:0]
R/W-0000000000000000b
Table 8-85 ADC1A_GCAL Register Field Descriptions
BitFieldTypeResetDescription
15:0GCAL1A[15:0]R/W0000000000000000bADC1A gain calibration bits [15:0]
Value provided in two's complement format.
LSB size = 1/216 = 0.000015
Mapping:
0111111111111111b = 1.499985
0000000000000001b = 1.000015
0000000000000000b = 1
1111111111111111b = 0.999985
1000000000000000b = 0.5

8.6.1.61 OCCA_CFG Register (Address = 87h) [Reset = 0000h]

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Figure 8-106 OCCA_CFG Register
15141312111098
OCCA_ENOCCA_POLRESERVEDOCCA_NUM[4:0]
R/W-0bR/W-0bR/W-0bR/W-00000b
76543210
RESERVED
R-00000000b
Table 8-86 OCCA_CFG Register Field Descriptions
BitFieldTypeResetDescription
15OCCA_ENR/W0bADC1A overcurrent comparator enable
Enables the digital fast filter and digital comparator on ADC1A. ADC1A must be enabled to use the overcurrent comparator. The fast filter is not affected by the STARTA and STOPA bits.
0b = Disabled
1b = Enabled
14OCCA_POLR/W0bOCCA pin polarity selection
Selects the polarity of the OCCA pin. The actual output behavior of the GPIO3/OCCA pin, when configured as OCCA output in the GPIO3_SRC bit, depends on the GPIO3_FMT setting. An OCCA fault is active when any of the OCCA_HTn or OCCA_LTn bits are active.
0b = Active low. In case of a fault a logic low level is driven.
1b = Active high. In case of a fault a logic high level is driven.
13RESERVEDR/W0bReserved
Always write 0b.
12:8OCCA_NUM[4:0]R/W00000bADC1A overcurrent comparator deglitch filter selection
Selects the number of conversions the output of the ADC1A digital fast filter must exceed the set high or low thresholds to trip the OCCA_HTn or OCCA_LTn comparator output. The fast filter path uses a SINC3 filter with a fixed OSR = 64. The counter starts again whenever the digital fast filter output falls below the threshold, means there is no hysteresis.
00000b = 1
00001b = 2
00010b = 3
00011b = 4
00100b = 5
00101b = 6
00110b = 7
00111b = 8
01000b = 9
01001b = 10
01010b = 12
01011b = 14
01100b = 16
01101b = 18
01110b = 20
01111b = 22
10000b = 24
10001b = 26
10010b = 28
10011b = 32
10100b = 40
10101b = 48
10110b = 56
10111b = 64
11000b = 72
11001b = 80
11010b = 88
11011b = 96
11100b = 104
11101b = 112
11110b = 120
11111b = 128
7:0RESERVEDR00000000bReserved
Always reads 00000000b

8.6.1.62 OCCA_HIGH_THRESHOLD Register (Address = 88h) [Reset = 7FFFh]

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Figure 8-107 OCCA_HIGH_THRESHOLD Register
15141312111098
OCCA_HIGH_TH[15:0]
R/W-0111111111111111b
76543210
OCCA_HIGH_TH[15:0]
R/W-0111111111111111b
Table 8-87 OCCA_HIGH_THRESHOLD Register Field Descriptions
BitFieldTypeResetDescription
15:0OCCA_HIGH_TH[15:0]R/W0111111111111111bADC1A overcurrent comparator high threshold bits [15:0]
Value provided in two's complement format.
LSB size = (2 x VREFA) / (GAIN1A x 216)
Values larger than the high threshold trigger an OCCA_HTn event. Setting the value to +FS (= 7FFFh) disables the high threshold detection.

8.6.1.63 OCCA_LOW_THRESHOLD Register (Address = 89h) [Reset = 8000h]

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Figure 8-108 OCCA_LOW_THRESHOLD Register
15141312111098
OCCA_LOW_TH[15:0]
R/W-1000000000000000b
76543210
OCCA_LOW_TH[15:0]
R/W-1000000000000000b
Table 8-88 OCCA_LOW_THRESHOLD Register Field Descriptions
BitFieldTypeResetDescription
15:0OCCA_LOW_TH[15:0]R/W1000000000000000bADC1A overcurrent comparator low threshold bits [15:0]
Value provided in two's complement format.
LSB size = (2 x VREFA) / (GAIN1A x 216)
Values smaller than the low threshold trigger an OCCA_LTn event. Setting the value to –FS (= 8000h) disables the low threshold detection.

8.6.1.64 SPARE_8Ah Register (Address = 8Ah) [Reset = 5555h]

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Figure 8-109 SPARE_8Ah Register
15141312111098
SPARE[15:0]
R/W-0101010101010101b
76543210
SPARE[15:0]
R/W-0101010101010101b
Table 8-89 SPARE_8Ah Register Field Descriptions
BitFieldTypeResetDescription
15:0SPARE[15:0]R/W0101010101010101bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.

8.6.1.65 ADC2A_CFG1 Register (Address = 8Bh) [Reset = 8010h]

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Figure 8-110 ADC2A_CFG1 Register
15141312111098
ADC2A_ENRESERVEDVCMA_ENOWD2A_SOURCE_MUX[2:0]
R/W-1bR-0000bR/W-0bR/W-000b
76543210
OWD2A_SOURCE_MUX[2:0]OWD2A_SINK_MUX[2:0]OWD2A_SOURCE_VALUE[1:0]OWD2A_SINK_VALUE[1:0]
R/W-000bR/W-001bR/W-00bR/W-00b
Table 8-90 ADC2A_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15ADC2A_ENR/W1bADC2A enable
Enables ADC2A.
Only change settings of registers from address 8Ch to 9Fh of ADC2A when ADC2A is disabled.
The conversion data of ADC2A reset to 0000h and the sequence counter SEQ2A_COUNT[1:0] resets to 00b when ADC2A is disabled or when the device is put in standby or power-down mode.
0b = Disabled
1b = Enabled
14:11RESERVEDR0000bReserved
Always reads 0000b.
10VCMA_ENR/W0bCommon-mode output buffer VCMA enable
Enables the common-mode output buffer VCMA on analog input V7A.
0b = Disabled
1b = Enabled
9:7OWD2A_SOURCE_MUX[2:0]R/W000bADC2A current source multiplexer selection
Selects the multiplexer channel for the ADC2A current source.
000b = V0A
001b = V1A
010b = V2A
011b = V3A
100b = V4A
101b = V5A
110b = V6A
111b = V7A
6:4OWD2A_SINK_MUX[2:0]R/W001bADC2A current sink multiplexer selection
Selects the multiplexer channel for the ADC2A current sink.
000b = V0A
001b = V1A
010b = V2A
011b = V3A
100b = V4A
101b = V5A
110b = V6A
111b = V7A
3:2OWD2A_SOURCE_VALUE[1:0]R/W00bADC2A current source value selection
Selects the current value for the ADC2A current source.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA
1:0OWD2A_SINK_VALUE[1:0]R/W00bADC2A current sink value selection
Selects the current value for the ADC2A current sink.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA

8.6.1.66 ADC2A_CFG2 Register (Address = 8Ch) [Reset = 0000h]

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Figure 8-111 ADC2A_CFG2 Register
15141312111098
SEQ2A_MODE[1:0]RESERVEDMUX2A_DELAY[2:0]
R/W-00bR-000bR/W-000b
76543210
RESERVEDOSR2A[1:0]
R-000000bR/W-00b
Table 8-91 ADC2A_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15:14SEQ2A_MODE[1:0]R/W00bADC2A sequencer mode selection
Selects the way the ADC2A sequencer starts a new sequence. Setting the SEQ2A_START bit always aborts and restarts an ongoing sequence in all modes.
00b = Single-shot sequence mode based on SEQ2A_START bit (ADC2A runs one time through the sequence after the SEQ2A_START bit is set)
01b = Single-shot sequence mode based on ADC1A conversion starts or SEQ2A_START bit. This setting is only useful when ADC1A is configured for continuous-conversion mode. Sequences are started at the falling edge of DRDYAn or when the SEQ2A_START bit is set. Conversion starts triggered by the DRDYAn signal are ignored, that is do not abort and restart a sequence, while a sequence is ongoing.
10b = Continuous sequence mode based on SEQ2A_START bit
11b = Continuous sequence mode based on SEQ2A_START bit
13:11RESERVEDR000bReserved
Always reads 00b.
10:8MUX2A_DELAY[2:0]R/W000bADC2A multiplexer delay time selection
Selects the delay time before starting conversion on the next sequence step.
000b = 16 x tMCLK (= 2 µs for fMCLK = 8.192 MHz)
001b = 64 x tMCLK (= 7.8 µs for fMCLK = 8.192 MHz)
010b = 128 x tMCLK (= 15.6 µs for fMCLK = 8.192 MHz)
011b = 256 x tMCLK (= 31.2 µs for fMCLK = 8.192 MHz)
100b = 512 x tMCLK (= 62.5 µs for fMCLK = 8.192 MHz)
101b = 1024 x tMCLK (= 124.9 µs for fMCLK = 8.192 MHz)
110b = 2048 x tMCLK (= 249.9 µs for fMCLK = 8.192 MHz)
111b = 4096 x tMCLK (= 499.7 µs for fMCLK = 8.192 MHz)
7:2RESERVEDR000000bReserved
Always reads 000000b.
1:0OSR2A[1:0]R/W00bADC2A oversampling ratio selection
Selects the oversampling ratio for ADC2A.
00b = 64 (SINC3 OSR = 64, conversion time = 384 x tMCLK)
01b = 128 (SINC3 OSR = 64, SINC1 OSR = 2, conversion time = 512 x tMCLK)
10b = 256 (SINC3 OSR = 64, SINC1 OSR = 4, conversion time = 768 x tMCLK)
11b = 512 (SINC3 OSR = 64, SINC1 OSR = 8, conversion time = 1280 x tMCLK)

8.6.1.67 SPARE_8Dh Register (Address = 8Dh) [Reset = 0000h]

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Figure 8-112 SPARE_8Dh Register
15141312111098
RESERVED
R-00000000b
76543210
SPARE[7:0]
R/W-00000000b
Table 8-92 SPARE_8Dh Register Field Descriptions
BitFieldTypeResetDescription
15:8RESERVEDR00000000bReserved
Always reads 00000000b.
7:0SPARE[7:0]R/W00000000bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.

8.6.1.68 ADC2A_OCAL Register (Address = 8Eh) [Reset = 0000h]

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Figure 8-113 ADC2A_OCAL Register
15141312111098
OCAL2A[15:0]
R/W-0000000000000000b
76543210
OCAL2A[15:0]
R/W-0000000000000000b
Table 8-93 ADC2A_OCAL Register Field Descriptions
BitFieldTypeResetDescription
15:0OCAL2A[15:0]R/W0000000000000000bADC2A offset calibration bits [15:0]
Value provided in two's complement format.
GAIN2A = 1: LSB size = (2 x VREFA) / 216
GAIN2A = 2, 4: LSB size = (2 x VREFA) / (2 x 216)

8.6.1.69 ADC2A_GCAL Register (Address = 8Fh) [Reset = 0000h]

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Figure 8-114 ADC2A_GCAL Register
15141312111098
GCAL2A[15:0]
R/W-0000000000000000b
76543210
GCAL2A[15:0]
R/W-0000000000000000b
Table 8-94 ADC2A_GCAL Register Field Descriptions
BitFieldTypeResetDescription
15:0GCAL2A[15:0]R/W0000000000000000bADC2A gain calibration bits [15:0]
Value provided in two's complement format.
LSB size = 1/216 = 0.000015
Mapping:
0111111111111111b = 1.499985
0000000000000001b = 1.000015
0000000000000000b = 1
1111111111111111b = 0.999985
1000000000000000b = 0.5

8.6.1.70 SEQ2A_STEP0_CFG Register (Address = 90h) [Reset = 0000h]

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Figure 8-115 SEQ2A_STEP0_CFG Register
15141312111098
SEQ2A_STEP0_ENSEQ2A_STEP0_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP0_CH_NSEQ2A_STEP0_CH_P[3:0]
R-00000000bR/W-0bR/W-0000b
Table 8-95 SEQ2A_STEP0_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP0_ENR/W0bADC2A sequence step 0 enable
Enables sequence step 0 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP0_GAIN[1:0]R/W00bADC2A sequence step 0 gain selection
Selects the gain of ADC2A for sequence step 0.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP0_CH_NR/W0bADC2A sequence step 0 negative input channel selection
Selects the negative ADC2A analog input for sequence step 0.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP0_CH_P[3:0]R/W0000bADC2A sequence step 0 positive input channel selection
Selects the positive ADC2A analog input for sequence step 0. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP0_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.71 SEQ2A_STEP1_CFG Register (Address = 91h) [Reset = 0001h]

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Figure 8-116 SEQ2A_STEP1_CFG Register
15141312111098
SEQ2A_STEP1_ENSEQ2A_STEP1_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP1_CH_NSEQ2A_STEP1_CH_P[3:0]
R-00000000bR/W-0bR/W-0001b
Table 8-96 SEQ2A_STEP1_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP1_ENR/W0bADC2A sequence step 1 enable
Enables sequence step 1 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP1_GAIN[1:0]R/W00bADC2A sequence step 1 gain selection
Selects the gain of ADC2A for sequence step 1.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP1_CH_NR/W0bADC2A sequence step 1 negative input channel selection
Selects the negative ADC2A analog input for sequence step 1.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP1_CH_P[3:0]R/W0001bADC2A sequence step 1 positive input channel selection
Selects the positive ADC2A analog input for sequence step 1. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP1_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.72 SEQ2A_STEP2_CFG Register (Address = 92h) [Reset = 0002h]

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Figure 8-117 SEQ2A_STEP2_CFG Register
15141312111098
SEQ2A_STEP2_ENSEQ2A_STEP2_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP2_CH_NSEQ2A_STEP2_CH_P[3:0]
R-00000000bR/W-0bR/W-0010b
Table 8-97 SEQ2A_STEP2_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP2_ENR/W0bADC2A sequence step 2 enable
Enables sequence step 2 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP2_GAIN[1:0]R/W00bADC2A sequence step 2 gain selection
Selects the gain of ADC2A for sequence step 2.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP2_CH_NR/W0bADC2A sequence step 2 negative input channel selection
Selects the negative ADC2A analog input for sequence step 2.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP2_CH_P[3:0]R/W0010bADC2A sequence step 2 positive input channel selection
Selects the positive ADC2A analog input for sequence step 2. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP2_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.73 SEQ2A_STEP3_CFG Register (Address = 93h) [Reset = 0003h]

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Figure 8-118 SEQ2A_STEP3_CFG Register
15141312111098
SEQ2A_STEP3_ENSEQ2A_STEP3_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP3_CH_NSEQ2A_STEP3_CH_P[3:0]
R-00000000bR/W-0bR/W-0011b
Table 8-98 SEQ2A_STEP3_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP3_ENR/W0bADC2A sequence step 3 enable
Enables sequence step 3 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP3_GAIN[1:0]R/W00bADC2A sequence step 3 gain selection
Selects the gain of ADC2A for sequence step 3.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP3_CH_NR/W0bADC2A sequence step 3 negative input channel selection
Selects the negative ADC2A analog input for sequence step 3.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP3_CH_P[3:0]R/W0011bADC2A sequence step 3 positive input channel selection
Selects the positive ADC2A analog input for sequence step 3. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP3_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.74 SEQ2A_STEP4_CFG Register (Address = 94h) [Reset = 0004h]

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Figure 8-119 SEQ2A_STEP4_CFG Register
15141312111098
SEQ2A_STEP4_ENSEQ2A_STEP4_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP4_CH_NSEQ2A_STEP4_CH_P[3:0]
R-00000000bR/W-0bR/W-0100b
Table 8-99 SEQ2A_STEP4_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP4_ENR/W0bADC2A sequence step 4 enable
Enables sequence step 4 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP4_GAIN[1:0]R/W00bADC2A sequence step 4 gain selection
Selects the gain of ADC2A for sequence step 4.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP4_CH_NR/W0bADC2A sequence step 4 negative input channel selection
Selects the negative ADC2A analog input for sequence step 4.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP4_CH_P[3:0]R/W0100bADC2A sequence step 4 positive input channel selection
Selects the positive ADC2A analog input for sequence step 4. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP4_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.75 SEQ2A_STEP5_CFG Register (Address = 95h) [Reset = 0005h]

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Figure 8-120 SEQ2A_STEP5_CFG Register
15141312111098
SEQ2A_STEP5_ENSEQ2A_STEP5_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP5_CH_NSEQ2A_STEP5_CH_P[3:0]
R-00000000bR/W-0bR/W-0101b
Table 8-100 SEQ2A_STEP5_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP5_ENR/W0bADC2A sequence step 5 enable
Enables sequence step 5 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP5_GAIN[1:0]R/W00bADC2A sequence step 5 gain selection
Selects the gain of ADC2A for sequence step 5.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP5_CH_NR/W0bADC2A sequence step 5 negative input channel selection
Selects the negative ADC2A analog input for sequence step 5.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP5_CH_P[3:0]R/W0101bADC2A sequence step 5 positive input channel selection
Selects the positive ADC2A analog input for sequence step 5. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP5_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.76 SEQ2A_STEP6_CFG Register (Address = 96h) [Reset = 0006h]

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Figure 8-121 SEQ2A_STEP6_CFG Register
15141312111098
SEQ2A_STEP6_ENSEQ2A_STEP6_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP6_CH_NSEQ2A_STEP6_CH_P[3:0]
R-00000000bR/W-0bR/W-0110b
Table 8-101 SEQ2A_STEP6_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP6_ENR/W0bADC2A sequence step 6 enable
Enables sequence step 6 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP6_GAIN[1:0]R/W00bADC2A sequence step 6 gain selection
Selects the gain of ADC2A for sequence step 6.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP6_CH_NR/W0bADC2A sequence step 6 negative input channel selection
Selects the negative ADC2A analog input for sequence step 6.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP6_CH_P[3:0]R/W0110bADC2A sequence step 6 positive input channel selection
Selects the positive ADC2A analog input for sequence step 6. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP6_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.77 SEQ2A_STEP7_CFG Register (Address = 97h) [Reset = 0007h]

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Figure 8-122 SEQ2A_STEP7_CFG Register
15141312111098
SEQ2A_STEP7_ENSEQ2A_STEP7_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP7_CH_NSEQ2A_STEP7_CH_P[3:0]
R-00000000bR/W-0bR/W-0111b
Table 8-102 SEQ2A_STEP7_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP7_ENR/W0bADC2A sequence step 7 enable
Enables sequence step 7 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP7_GAIN[1:0]R/W00bADC2A sequence step 7 gain selection
Selects the gain of ADC2A for sequence step 7.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP7_CH_NR/W0bADC2A sequence step 7 negative input channel selection
Selects the negative ADC2A analog input for sequence step 7.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP7_CH_P[3:0]R/W0111bADC2A sequence step 7 positive input channel selection
Selects the positive ADC2A analog input for sequence step 7. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP7_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.78 SEQ2A_STEP8_CFG Register (Address = 98h) [Reset = 0008h]

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Figure 8-123 SEQ2A_STEP8_CFG Register
15141312111098
SEQ2A_STEP8_ENSEQ2A_STEP8_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP8_CH_NSEQ2A_STEP8_CH_P[3:0]
R-00000000bR/W-0bR/W-1000b
Table 8-103 SEQ2A_STEP8_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP8_ENR/W0bADC2A sequence step 8 enable
Enables sequence step 8 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP8_GAIN[1:0]R/W00bADC2A sequence step 8 gain selection
Selects the gain of ADC2A for sequence step 8.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP8_CH_NR/W0bADC2A sequence step 8 negative input channel selection
Selects the negative ADC2A analog input for sequence step 8.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP8_CH_P[3:0]R/W1000bADC2A sequence step 8 positive input channel selection
Selects the positive ADC2A analog input for sequence step 8. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP8_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.79 SEQ2A_STEP9_CFG Register (Address = 99h) [Reset = 0009h]

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Figure 8-124 SEQ2A_STEP9_CFG Register
15141312111098
SEQ2A_STEP9_ENSEQ2A_STEP9_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP9_CH_NSEQ2A_STEP9_CH_P[3:0]
R-00000000bR/W-0bR/W-1001b
Table 8-104 SEQ2A_STEP9_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP9_ENR/W0bADC2A sequence step 9 enable
Enables sequence step 9 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP9_GAIN[1:0]R/W00bADC2A sequence step 9 gain selection
Selects the gain of ADC2A for sequence step 9.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP9_CH_NR/W0bADC2A sequence step 9 negative input channel selection
Selects the negative ADC2A analog input for sequence step 9.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP9_CH_P[3:0]R/W1001bADC2A sequence step 9 positive input channel selection
Selects the positive ADC2A analog input for sequence step 9. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP9_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.80 SEQ2A_STEP10_CFG Register (Address = 9Ah) [Reset = 000Ah]

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Figure 8-125 SEQ2A_STEP10_CFG Register
15141312111098
SEQ2A_STEP10_ENSEQ2A_STEP10_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP10_CH_NSEQ2A_STEP10_CH_P[3:0]
R-00000000bR/W-0bR/W-1010b
Table 8-105 SEQ2A_STEP10_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP10_ENR/W0bADC2A sequence step 10 enable
Enables sequence step 10 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP10_GAIN[1:0]R/W00bADC2A sequence step 10 gain selection
Selects the gain of ADC2A for sequence step 10.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP10_CH_NR/W0bADC2A sequence step 10 negative input channel selection
Selects the negative ADC2A analog input for sequence step 10.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP10_CH_P[3:0]R/W1010bADC2A sequence step 10 positive input channel selection
Selects the positive ADC2A analog input for sequence step 10. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP10_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.81 SEQ2A_STEP11_CFG Register (Address = 9Bh) [Reset = 000Bh]

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Figure 8-126 SEQ2A_STEP11_CFG Register
15141312111098
SEQ2A_STEP11_ENSEQ2A_STEP11_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP11_CH_NSEQ2A_STEP11_CH_P[3:0]
R-00000000bR/W-0bR/W-1011b
Table 8-106 SEQ2A_STEP11_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP11_ENR/W0bADC2A sequence step 11 enable
Enables sequence step 11 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP11_GAIN[1:0]R/W00bADC2A sequence step 11 gain selection
Selects the gain of ADC2A for sequence step 11.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP11_CH_NR/W0bADC2A sequence step 11 negative input channel selection
Selects the negative ADC2A analog input for sequence step 11.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP11_CH_P[3:0]R/W1011bADC2A sequence step 11 positive input channel selection
Selects the positive ADC2A analog input for sequence step 11. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP11_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.82 SEQ2A_STEP12_CFG Register (Address = 9Ch) [Reset = 000Ch]

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Figure 8-127 SEQ2A_STEP12_CFG Register
15141312111098
SEQ2A_STEP12_ENSEQ2A_STEP12_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP12_CH_NSEQ2A_STEP12_CH_P[3:0]
R-00000000bR/W-0bR/W-1100b
Table 8-107 SEQ2A_STEP12_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP12_ENR/W0bADC2A sequence step 12 enable
Enables sequence step 12 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP12_GAIN[1:0]R/W00bADC2A sequence step 12 gain selection
Selects the gain of ADC2A for sequence step 12.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP12_CH_NR/W0bADC2A sequence step 12 negative input channel selection
Selects the negative ADC2A analog input for sequence step 12.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP12_CH_P[3:0]R/W1100bADC2A sequence step 12 positive input channel selection
Selects the positive ADC2A analog input for sequence step 12. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP12_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.83 SEQ2A_STEP13_CFG Register (Address = 9Dh) [Reset = 000Dh]

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Figure 8-128 SEQ2A_STEP13_CFG Register
15141312111098
SEQ2A_STEP13_ENSEQ2A_STEP13_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP13_CH_NSEQ2A_STEP13_CH_P[3:0]
R-00000000bR/W-0bR/W-1101b
Table 8-108 SEQ2A_STEP13_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP13_ENR/W0bADC2A sequence step 13 enable
Enables sequence step 13 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP13_GAIN[1:0]R/W00bADC2A sequence step 13 gain selection
Selects the gain of ADC2A for sequence step 13.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP13_CH_NR/W0bADC2A sequence step 13 negative input channel selection
Selects the negative ADC2A analog input for sequence step 13.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP13_CH_P[3:0]R/W1101bADC2A sequence step 13 positive input channel selection
Selects the positive ADC2A analog input for sequence step 13. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP13_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.84 SEQ2A_STEP14_CFG Register (Address = 9Eh) [Reset = 000Eh]

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Figure 8-129 SEQ2A_STEP14_CFG Register
15141312111098
SEQ2A_STEP14_ENSEQ2A_STEP14_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP14_CH_NSEQ2A_STEP14_CH_P[3:0]
R-00000000bR/W-0bR/W-1110b
Table 8-109 SEQ2A_STEP14_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP14_ENR/W0bADC2A sequence step 14 enable
Enables sequence step 14 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP14_GAIN[1:0]R/W00bADC2A sequence step 14 gain selection
Selects the gain of ADC2A for sequence step 14.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP14_CH_NR/W0bADC2A sequence step 14 negative input channel selection
Selects the negative ADC2A analog input for sequence step 14.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP14_CH_P[3:0]R/W1110bADC2A sequence step 14 positive input channel selection
Selects the positive ADC2A analog input for sequence step 14. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP14_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.85 SEQ2A_STEP15_CFG Register (Address = 9Fh) [Reset = 000Fh]

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Figure 8-130 SEQ2A_STEP15_CFG Register
15141312111098
SEQ2A_STEP15_ENSEQ2A_STEP15_GAIN[1:0]RESERVED
R/W-0bR/W-00bR-00000000b
76543210
RESERVEDSEQ2A_STEP15_CH_NSEQ2A_STEP15_CH_P[3:0]
R-00000000bR/W-0bR/W-1111b
Table 8-110 SEQ2A_STEP15_CFG Register Field Descriptions
BitFieldTypeResetDescription
15SEQ2A_STEP15_ENR/W0bADC2A sequence step 15 enable
Enables sequence step 15 of the ADC2A sequencer.
0b = Disabled
1b = Enabled
14:13SEQ2A_STEP15_GAIN[1:0]R/W00bADC2A sequence step 15 gain selection
Selects the gain of ADC2A for sequence step 15.
00b = 1
01b = 2
10b = 4
11b = 4
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4SEQ2A_STEP15_CH_NR/W0bADC2A sequence step 15 negative input channel selection
Selects the negative ADC2A analog input for sequence step 15.
0b = AGNDA
1b = V7A
3:0SEQ2A_STEP15_CH_P[3:0]R/W1111bADC2A sequence step 15 positive input channel selection
Selects the positive ADC2A analog input for sequence step 15. For settings where the negative ADC input is automatically selected, the SEQ2A_STEP15_CH_N bit has no effect.
0000b = V0A
0001b = V1A
0010b = V2A
0011b = V3A
0100b = V4A
0101b = V5A
0110b = V6A
0111b = V7A
1000b = Temperature sensor A (negative ADC input is automatically selected)
1001b = Internal short to AGNDA, disconnected from inputs (negative ADC input is automatically selected)
1010b = Test DAC B (negative ADC input is automatically selected)
1011b = AVDD/4 (negative ADC input is automatically selected)
1100b = IOVDD/4 (negative ADC input is automatically selected)
1101b = DVDD/2 (negative ADC input is automatically selected)
1110b = APWR/103 (negative ADC input is automatically selected)
1111b = DPWR/103 (negative ADC input is automatically selected)

8.6.1.86 SPARE_A0h Register (Address = A0h) [Reset = 0210h]

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Figure 8-131 SPARE_A0h Register
15141312111098
RESERVEDSPARE[1:0]RESERVED
R-0000bR/W-00bR-1000b
76543210
RESERVEDSPARE[1:0]RESERVED
R-1000bR/W-01bR-0000b
Table 8-111 SPARE_A0h Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0000bReserved
Always reads 0000b.
11:10SPARE[1:0]R/W00bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.
9:6RESERVEDR1000bReserved
Always reads 1000b.
5:4SPARE[1:0]R/W01bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.
3:0RESERVEDR0000bReserved
Always reads 0000b.

8.6.1.87 SPARE_A1h Register (Address = A1h) [Reset = 0000h]

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Figure 8-132 SPARE_A1h Register
15141312111098
SPARE[15:0]
R/W-0000000000000000b
76543210
SPARE[15:0]
R/W-0000000000000000b
Table 8-112 SPARE_A1h Register Field Descriptions
BitFieldTypeResetDescription
15:0SPARE[15:0]R/W0000000000000000bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.

8.6.1.88 SPARE_A2h Register (Address = A2h) [Reset = 0000h]

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Figure 8-133 SPARE_A2h Register
15141312111098
SPARE[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-113 SPARE_A2h Register Field Descriptions
BitFieldTypeResetDescription
15:8SPARE[7:0]R/W00000000bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.
7:0RESERVEDR00000000bReserved
Always reads 00000000b.

8.6.1.89 SPARE_A3h Register (Address = A3h) [Reset = 0000h]

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Figure 8-134 SPARE_A3h Register
15141312111098
SPARE[15:0]
R/W-0000000000000000b
76543210
SPARE[15:0]
R/W-0000000000000000b
Table 8-114 SPARE_A3h Register Field Descriptions
BitFieldTypeResetDescription
15:0SPARE[15:0]R/W0000000000000000bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.

8.6.1.90 REGISTER_MAP2_CRC Register (Address = BEh) [Reset = 0000h]

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Figure 8-135 REGISTER_MAP2_CRC Register
15141312111098
REG_MAP2_CRC_VALUE[15:0]
R/W-0000000000000000b
76543210
REG_MAP2_CRC_VALUE[15:0]
R/W-0000000000000000b
Table 8-115 REGISTER_MAP2_CRC Register Field Descriptions
BitFieldTypeResetDescription
15:0REG_MAP2_CRC_VALUE[15:0]R/W0000000000000000bRegister map CRC value for section 2
Register map CRC value for section 2.

8.6.1.91 REGMAP3_TDACB_CFG Register (Address = C0h) [Reset = 0000h]

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Figure 8-136 REGMAP3_TDACB_CFG Register
15141312111098
REG_MAP3_CRC_ENRESERVED
R/W-0bR-000000000000b
76543210
RESERVEDTDACB_VALUE[2:0]
R-000000000000bR/W-000b
Table 8-116 REGMAP3_TDACB_CFG Register Field Descriptions
BitFieldTypeResetDescription
15REG_MAP3_CRC_ENR/W0bRegister map section 3 CRC enable
Enables the register map CRC for section 3 (register address space from C0h to E3h).
0b = Disabled
1b = Enabled
14:3RESERVEDR000000000000bReserved
Always reads 000000000000b.
2:0TDACB_VALUE[2:0]R/W000bTest DAC B output value
Selects the output value of Test DAC B.
000b = 1 x VREFB/40
001b = 2 x VREFB/40
010b = 4 x VREFB/40
011b = 9 x VREFB/40
100b = 18 x VREFB/40
101b = 36 x VREFB/40
110b = –4 x VREFB/40
111b = –9 x VREFB/40

8.6.1.92 GPIOB_CFG Register (Address = C1h) [Reset = 8000h]

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Figure 8-137 GPIOB_CFG Register
15141312111098
RESERVEDSPARE[2:0]GPIO1B_FMTGPIO0B_FMTGPIO1B_DIRGPIO0B_DIR
R-1bR/W-000bR/W-0bR/W-0bR/W-0bR/W-0b
76543210
GPIO1B_PWM_TB[1:0]GPIO0B_PWM_TB[1:0]SPARE[1:0]GPO1B_DATGPO0B_DAT
R/W-00bR/W-00bR/W-00bR/W-0bR/W-0b
Table 8-117 GPIOB_CFG Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR1bReserved
Always reads 1b.
14:12SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.
11GPIO1B_FMTR/W0bGPIO1B format
Configures GPIO1B for static input and output levels or for PWM input levels.
0b = When GPIO1B is configured as a digital input: Logic levels are based on static input levels. When GPIO1B is configured as a digital output: Output with static output levels.
1b = When GPIO1B is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO1B is configured as a digital output: Output with static output levels. GPIO1B does not have PWM output capability.
10GPIO0B_FMTR/W0bGPIO0B format
Configures GPIO0B for static input and output levels or for PWM input levels.
0b = When GPIO0B is configured as a digital input: Logic levels are based on static input levels. When GPIO0B is configured as a digital output: Output with static output levels.
1b = When GPIO0B is configured as a digital input: Logic levels are based on PWM input decoding. When GPIO0B is configured as a digital output: Output with static output levels. GPIO0B does not have PWM output capability.
9GPIO1B_DIRR/W0bGPIO1B direction
Configures GPIO1B as a digital input or digital output.
0b = Digital input
1b = Digital output
8GPIO0B_DIRR/W0bGPIO0B direction
Configures GPIO0B as a digital input or digital output.
0b = Digital input
1b = Digital output
7:6GPIO1B_PWM_TB[1:0]R/W00bGPIO1B PWM time base selection
Selects the time base used for the PWM encoder when GPIO1B is configured as a digital input.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
5:4GPIO0B_PWM_TB[1:0]R/W00bGPIO0B PWM time base selection
Selects the time base used for the PWM encoder when GPIO0B is configured as a digital input.
00b = 16 x tMCLK (= 1/512 kHz for fMCLK = 8.192 MHz)
01b = 64 x tMCLK (= 1/128 kHz for fMCLK = 8.192 MHz)
10b = 256 x tMCLK (= 1/32 kHz for fMCLK = 8.192 MHz)
11b = 1024 x tMCLK (= 1/8 kHz for fMCLK = 8.192 MHz)
3:2SPARE[1:0]R/W00bSpare bits
Provided as R/W bits as a means to check the register map section 2 CRC. Bit settings have no effect.
1GPO1B_DATR/W0bGPIO1B output data
Output value of GPIO1B when configured as an output. Bit setting has not effect when GPIO1B is configured as a digital input.
0b = Low
1b = High
0GPO0B_DATR/W0bGPIO0B output data
Output value of GPIO0B when configured as an output. Bit setting has not effect when GPIO0B is configured as a digital input.
0b = Low
1b = High

8.6.1.93 ADC1B_CFG1 Register (Address = C2h) [Reset = 0400h]

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Figure 8-138 ADC1B_CFG1 Register
15141312111098
RESERVEDCONV_MODE1BOSR1B[2:0]
R-0000bR/W-0bR/W-100b
76543210
RESERVEDGC1B_ENGC1B_DELAY[2:0]
R-0000bR/W-0bR/W-000b
Table 8-118 ADC1B_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0000bReserved
Always reads 0000b.
11CONV_MODE1BR/W0bConversion mode selection
Selects the conversion mode for ADC1B.
0b = Continuous-conversion mode
1b = Single-shot conversion mode
10:8OSR1B[2:0]R/W100bOversampling ratio selection
Selects the oversampling ratio for ADC1B. The data rate calculates to fMOD / OSR.
000b = 64
001b = 128
010b = 256
011b = 512
100b = 1024
101b = 2048
110b = 4096
111b = 8192
7:4RESERVEDR0000bReserved
Always reads 0000b.
3GC1B_ENR/W0bGlobal-chop mode enable
Enables the global-chop mode for ADC1B.
0b = Disabled
1b = Enabled
2:0GC1B_DELAY[2:0]R/W000bGlobal-chop mode delay time selection
Selects the delay time in global-chop mode for ADC1B.
000b = 2 x tMOD
001b = 4 x tMOD
010b = 8 x tMOD
011b = 16 x tMOD
100b = 32 x tMOD
101b = 64 x tMOD
110b = 128 x tMOD
111b = 256 x tMOD

8.6.1.94 ADC1B_CFG2 Register (Address = C3h) [Reset = 8010h]

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Figure 8-139 ADC1B_CFG2 Register
15141312111098
ADC1B_ENRESERVEDGAIN1B[1:0]MUX1B[1:0]
R/W-1bR-000bR/W-00bR/W-00b
76543210
RESERVEDOWD1B_SOURCE_MUXOWD1B_SINK_MUXOWD1B_SOURCE_VALUE[1:0]OWD1B_SINK_VALUE[1:0]
R-00bR/W-0bR/W-1bR/W-00bR/W-00b
Table 8-119 ADC1B_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
15ADC1B_ENR/W1bADC1B enable
Enables ADC1B.
The conversion data of ADC1B reset to 000000h and the conversion counter CONV1B_COUNT[1:0] resets to 00b when ADC1B is disabled or when the device is put in standby or power-down mode..
0b = Disabled
1b = Enabled
14:12RESERVEDR000bReserved
Always reads 000b.
11:10GAIN1B[1:0]R/W00bADC1B gain selection
Selects the gain (FSR = full scale range) of ADC1B. Gains 16 and 32 are digital gains using analog gain = 8.
00b = 4
01b = 8
10b = 16
11b = 32
9:8MUX1B[1:0]R/W00bADC1B multiplexer channel selection
Selects the multiplexer channel for ADC1B.
00b = AINp = CPB, AINn = CNB
01b = AINp = CNB, AINn = CPB
10b = Internal short to AGNDB. Analog inputs CPB, CNB disconnected from ADC1B.
11b = Test DAC A output
7:6RESERVEDR00bReserved
Always reads 00b.
5OWD1B_SOURCE_MUXR/W0bADC1B current source multiplexer selection
Selects the multiplexer channel for the ADC1B current source.
0b = CPB
1b = CNB
4OWD1B_SINK_MUXR/W1bADC1B current sink multiplexer selection
Selects the multiplexer channel for the ADC1B current sink.
0b = CPB
1b = CNB
3:2OWD1B_SOURCE_VALUE[1:0]R/W00bADC1B current source value selection
Selects the current value for the ADC1B current source.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA
1:0OWD1B_SINK_VALUE[1:0]R/W00bADC1B current sink value selection
Selects the current value for the ADC1B current sink.
00b = Off
01b = 4 µA
10b = 40 µA
11b = 240 µA

8.6.1.95 ADC1B_OCAL_MSB Register (Address = C4h) [Reset = 0000h]

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Figure 8-140 ADC1B_OCAL_MSB Register
15141312111098
OCAL1B[23:8]
R/W-0000000000000000b
76543210
OCAL1B[23:8]
R/W-0000000000000000b
Table 8-120 ADC1B_OCAL_MSB Register Field Descriptions
BitFieldTypeResetDescription
15:0OCAL1B[23:8]R/W0000000000000000bADC1B offset calibration bits [23:8]
Value provided in two's complement format.
LSB size = (2 x VREFB) / (GAIN1B x 224)

8.6.1.96 ADC1B_OCAL_LSB Register (Address = C5h) [Reset = 0000h]

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Figure 8-141 ADC1B_OCAL_LSB Register
15141312111098
OCAL1B[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-121 ADC1B_OCAL_LSB Register Field Descriptions
BitFieldTypeResetDescription
15:8OCAL1B[7:0]R/W00000000bADC1B offset calibration bits [7:0]
Value provided in two's complement format.
LSB size = (2 x VREFB) / (GAIN1B x 224)
7:0RESERVEDR00000000bReserved
Always reads 00000000b.

8.6.1.97 ADC1B_GCAL Register (Address = C6h) [Reset = 0000h]

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Figure 8-142 ADC1B_GCAL Register
15141312111098
GCAL1B[15:0]
R/W-0000000000000000b
76543210
GCAL1B[15:0]
R/W-0000000000000000b
Table 8-122 ADC1B_GCAL Register Field Descriptions
BitFieldTypeResetDescription
15:0GCAL1B[15:0]R/W0000000000000000bADC1B gain calibration bits [15:0]
Value provided in two's complement format.
LSB size = 1/216 = 0.000015
Mapping:
0111111111111111b = 1.499985
0000000000000001b = 1.000015
0000000000000000b = 1
1111111111111111b = 0.999985
1000000000000000b = 0.5

8.6.1.98 OCCB_CFG Register (Address = C7h) [Reset = 0000h]

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Figure 8-143 OCCB_CFG Register
15141312111098
OCCB_ENOCCB_POLRESERVEDOCCB_NUM[4:0]
R/W-0bR/W-0bR/W-0bR/W-00000b
76543210
RESERVED
R-00000000b
Table 8-123 OCCB_CFG Register Field Descriptions
BitFieldTypeResetDescription
15OCCB_ENR/W0bADC1B overcurrent comparator enable
Enables the digital fast filter and digital comparator on ADC1B. ADC1B must be enabled to use the overcurrent comparator. The fast filter is not affected by the STARTB and STOPB bits.
0b = Disabled
1b = Enabled
14OCCB_POLR/W0bOCCB pin polarity selection
Selects the polarity of the OCCB pin. The actual output behavior of the GPIO4/OCCB pin, when configured as OCCB output in the GPIO4_SRC bit, depends on the GPIO4_FMT setting. An OCCB fault is active when any of the OCCB_HTn or OCCB_LTn bits are active.
0b = Active low. In case of a fault a logic low level is driven.
1b = Active high. In case of a fault a logic high level is driven.
13RESERVEDR/W0bReserved
Always write 0b.
12:8OCCB_NUM[4:0]R/W00000bADC1B overcurrent comparator deglitch filter selection
Selects the number of conversions the output of the ADC1B digital fast filter must exceed the set high or low thresholds to trip the OCCB_HTn or OCCB_LTn comparator output. The fast filter path uses a SINC3 filter with a fixed OSR = 64. The counter starts again whenever the digital fast filter output falls below the threshold, means there is no hysteresis.
00000b = 1
00001b = 2
00010b = 3
00011b = 4
00100b = 5
00101b = 6
00110b = 7
00111b = 8
01000b = 9
01001b = 10
01010b = 12
01011b = 14
01100b = 16
01101b = 18
01110b = 20
01111b = 22
10000b = 24
10001b = 26
10010b = 28
10011b = 32
10100b = 40
10101b = 48
10110b = 56
10111b = 64
11000b = 72
11001b = 80
11010b = 88
11011b = 96
11100b = 104
11101b = 112
11110b = 120
11111b = 128
7:0RESERVEDR00000000bReserved
Always reads 00000000b.

8.6.1.99 OCCB_HIGH_THRESHOLD Register (Address = C8h) [Reset = 7FFFh]

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Figure 8-144 OCCB_HIGH_THRESHOLD Register
15141312111098
OCCB_HIGH_TH[15:0]
R/W-0111111111111111b
76543210
OCCB_HIGH_TH[15:0]
R/W-0111111111111111b
Table 8-124 OCCB_HIGH_THRESHOLD Register Field Descriptions
BitFieldTypeResetDescription
15:0OCCB_HIGH_TH[15:0]R/W0111111111111111bADC1B overcurrent comparator high threshold bits [15:0]
Value provided in two's complement format.
LSB size = (2 x VREFB) / (GAIN1B x 216)
Values larger than the high threshold trigger an OCCB_HTn event. Setting the value to +FS (= 7FFFh) disables the high threshold detection.

8.6.1.100 OCCB_LOW_THRESHOLD Register (Address = C9h) [Reset = 8000h]

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Figure 8-145 OCCB_LOW_THRESHOLD Register
15141312111098
OCCB_LOW_TH[15:0]
R/W-1000000000000000b
76543210
OCCB_LOW_TH[15:0]
R/W-1000000000000000b
Table 8-125 OCCB_LOW_THRESHOLD Register Field Descriptions
BitFieldTypeResetDescription
15:0OCCB_LOW_TH[15:0]R/W1000000000000000bADC1B overcurrent comparator low threshold bits [15:0]
Value provided in two's complement format.
LSB size = (2 x VREFB) / (GAIN1B x 216)
Values smaller than the low threshold trigger an OCCB_LTn event. Setting the value to –FS (= 8000h) disables the low threshold detection.

8.6.1.101 SPARE_CAh Register (Address = CAh) [Reset = 5555h]

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Figure 8-146 SPARE_CAh Register
15141312111098
SPARE[15:0]
R/W-0101010101010101b
76543210
SPARE[15:0]
R/W-0101010101010101b
Table 8-126 SPARE_CAh Register Field Descriptions
BitFieldTypeResetDescription
15:0SPARE[15:0]R/W0101010101010101bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.102 SPARE_CBh Register (Address = CBh) [Reset = 0010h]

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Figure 8-147 SPARE_CBh Register
15141312111098
RESERVEDSPARE[6:0]
R-00000bR/W-0000001b
76543210
SPARE[6:0]RESERVED
R/W-0000001bR-0000b
Table 8-127 SPARE_CBh Register Field Descriptions
BitFieldTypeResetDescription
15:11RESERVEDR00000bReserved
Always reads 00000b.
10:4SPARE[6:0]R/W0000001bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
3:0RESERVEDR0000bReserved
Always reads 0000b.

8.6.1.103 SPARE_CCh Register (Address = CCh) [Reset = 0000h]

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Figure 8-148 SPARE_CCh Register
15141312111098
SPARE[1:0]RESERVEDSPARE[2:0]
R/W-00bR-000bR/W-000b
76543210
RESERVEDSPARE[1:0]
R-000000bR/W-00b
Table 8-128 SPARE_CCh Register Field Descriptions
BitFieldTypeResetDescription
15:14SPARE[1:0]R/W00bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
13:11RESERVEDR000bReserved
Always reads 00b.
10:8SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
7:2RESERVEDR000000bReserved
Always reads 000000b.
1:0SPARE[1:0]R/W00bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.104 SPARE_CDh Register (Address = CDh) [Reset = 0000h]

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Figure 8-149 SPARE_CDh Register
15141312111098
RESERVED
R-00000000b
76543210
SPARE[7:0]
R/W-00000000b
Table 8-129 SPARE_CDh Register Field Descriptions
BitFieldTypeResetDescription
15:8RESERVEDR00000000bReserved
Always reads 00000000b.
7:0SPARE[7:0]R/W00000000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.105 SPARE_CEh Register (Address = CEh) [Reset = 0000h]

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Figure 8-150 SPARE_CEh Register
15141312111098
SPARE[15:0]
R/W-0000000000000000b
76543210
SPARE[15:0]
R/W-0000000000000000b
Table 8-130 SPARE_CEh Register Field Descriptions
BitFieldTypeResetDescription
15:0SPARE[15:0]R/W0000000000000000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.106 SPARE_CFh Register (Address = CFh) [Reset = 0000h]

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Figure 8-151 SPARE_CFh Register
15141312111098
SPARE[15:0]
R/W-0000000000000000b
76543210
SPARE[15:0]
R/W-0000000000000000b
Table 8-131 SPARE_CFh Register Field Descriptions
BitFieldTypeResetDescription
15:0SPARE[15:0]R/W0000000000000000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.107 SPARE_D0h Register (Address = D0h) [Reset = 0000h]

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Figure 8-152 SPARE_D0h Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-00000b
Table 8-132 SPARE_D0h Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W00000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.108 SPARE_D1h Register (Address = D1h) [Reset = 0001h]

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Figure 8-153 SPARE_D1h Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-00001b
Table 8-133 SPARE_D1h Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W00001bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.109 SPARE_D2h Register (Address = D2h) [Reset = 0002h]

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Figure 8-154 SPARE_D2h Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-00010b
Table 8-134 SPARE_D2h Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W00010bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.110 SPARE_D3h Register (Address = D3h) [Reset = 0003h]

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Figure 8-155 SPARE_D3h Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-00011b
Table 8-135 SPARE_D3h Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W00011bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.111 SPARE_D4h Register (Address = D4h) [Reset = 0004h]

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Figure 8-156 SPARE_D4h Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-00100b
Table 8-136 SPARE_D4h Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W00100bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.112 SPARE_D5h Register (Address = D5h) [Reset = 0005h]

Return to the Summary Table.

Figure 8-157 SPARE_D5h Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-00101b
Table 8-137 SPARE_D5h Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W00101bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.113 SPARE_D6h Register (Address = D6h) [Reset = 0006h]

Return to the Summary Table.

Figure 8-158 SPARE_D6h Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-00110b
Table 8-138 SPARE_D6h Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W00110bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.114 SPARE_D7h Register (Address = D7h) [Reset = 0007h]

Return to the Summary Table.

Figure 8-159 SPARE_D7h Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-00111b
Table 8-139 SPARE_D7h Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W00111bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.115 SPARE_D8h Register (Address = D8h) [Reset = 0008h]

Return to the Summary Table.

Figure 8-160 SPARE_D8h Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-01000b
Table 8-140 SPARE_D8h Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W01000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.116 SPARE_D9h Register (Address = D9h) [Reset = 0009h]

Return to the Summary Table.

Figure 8-161 SPARE_D9h Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-01001b
Table 8-141 SPARE_D9h Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W01001bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.117 SPARE_DAh Register (Address = DAh) [Reset = 000Ah]

Return to the Summary Table.

Figure 8-162 SPARE_DAh Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-01010b
Table 8-142 SPARE_DAh Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W01010bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.118 SPARE_DBh Register (Address = DBh) [Reset = 000Bh]

Return to the Summary Table.

Figure 8-163 SPARE_DBh Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-01011b
Table 8-143 SPARE_DBh Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W01011bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.119 SPARE_DCh Register (Address = DCh) [Reset = 000Ch]

Return to the Summary Table.

Figure 8-164 SPARE_DCh Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-01100b
Table 8-144 SPARE_DCh Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W01100bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.120 SPARE_DDh Register (Address = DDh) [Reset = 000Dh]

Return to the Summary Table.

Figure 8-165 SPARE_DDh Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-01101b
Table 8-145 SPARE_DDh Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W01101bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.121 SPARE_DEh Register (Address = DEh) [Reset = 000Eh]

Return to the Summary Table.

Figure 8-166 SPARE_DEh Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-01110b
Table 8-146 SPARE_DEh Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W01110bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.122 SPARE_DFh Register (Address = DFh) [Reset = 000Fh]

Return to the Summary Table.

Figure 8-167 SPARE_DFh Register
15141312111098
SPARE[2:0]RESERVED
R/W-000bR-00000000b
76543210
RESERVEDSPARE[4:0]
R-00000000bR/W-01111b
Table 8-147 SPARE_DFh Register Field Descriptions
BitFieldTypeResetDescription
15:13SPARE[2:0]R/W000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
12:5RESERVEDR00000000bReserved
Always reads 00000000b.
4:0SPARE[4:0]R/W01111bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.123 SPARE_E0h Register (Address = E0h) [Reset = 0210h]

Return to the Summary Table.

Figure 8-168 SPARE_E0h Register
15141312111098
RESERVEDSPARE[1:0]RESERVED
R-0000bR/W-00bR-1000b
76543210
RESERVEDSPARE[1:0]RESERVED
R-1000bR/W-01bR-0000b
Table 8-148 SPARE_E0h Register Field Descriptions
BitFieldTypeResetDescription
15:12RESERVEDR0000bReserved
Always reads 0000b.
11:10SPARE[1:0]R/W00bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
9:6RESERVEDR1000bReserved
Always reads 1000b.
5:4SPARE[1:0]R/W01bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
3:0RESERVEDR0000bReserved
Always reads 0000b.

8.6.1.124 SPARE_E1h Register (Address = E1h) [Reset = 0000h]

Return to the Summary Table.

Figure 8-169 SPARE_E1h Register
15141312111098
SPARE[15:0]
R/W-0000000000000000b
76543210
SPARE[15:0]
R/W-0000000000000000b
Table 8-149 SPARE_E1h Register Field Descriptions
BitFieldTypeResetDescription
15:0SPARE[15:0]R/W0000000000000000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.125 SPARE_E2h Register (Address = E2h) [Reset = 0000h]

Return to the Summary Table.

Figure 8-170 SPARE_E2h Register
15141312111098
SPARE[7:0]
R/W-00000000b
76543210
RESERVED
R-00000000b
Table 8-150 SPARE_E2h Register Field Descriptions
BitFieldTypeResetDescription
15:8SPARE[7:0]R/W00000000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.
7:0RESERVEDR00000000bReserved
Always reads 0x00.

8.6.1.126 SPARE_E3h Register (Address = E3h) [Reset = 0000h]

Return to the Summary Table.

Figure 8-171 SPARE_E3h Register
15141312111098
SPARE[15:0]
R/W-0000000000000000b
76543210
SPARE[15:0]
R/W-0000000000000000b
Table 8-151 SPARE_E3h Register Field Descriptions
BitFieldTypeResetDescription
15:0SPARE[15:0]R/W0000000000000000bSpare bits
Provided as R/W bits as a means to check the register map section 3 CRC. Bit settings have no effect.

8.6.1.127 REGISTER_MAP3_CRC Register (Address = FEh) [Reset = 0000h]

Return to the Summary Table.

Figure 8-172 REGISTER_MAP3_CRC Register
15141312111098
REG_MAP3_CRC_VALUE[15:0]
R/W-0000000000000000b
76543210
REG_MAP3_CRC_VALUE[15:0]
R/W-0000000000000000b
Table 8-152 REGISTER_MAP3_CRC Register Field Descriptions
BitFieldTypeResetDescription
15:0REG_MAP3_CRC_VALUE[15:0]R/W0000000000000000bRegister map CRC value for section 3
Register map CRC value for section 3.