SBASAE7 August   2022 ADS131M02-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Filter
        1. 8.3.7.1 Digital Filter Implementation
          1. 8.3.7.1.1 Fast-Settling Filter
          2. 8.3.7.1.2 SINC3 and SINC3 + SINC1 Filter
        2. 8.3.7.2 Digital Filter Characteristic
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Communication Cyclic Redundancy Check (CRC)
      13. 8.3.13 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 SYNC/RESET Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Fast Start-Up Behavior
      3. 8.4.3 Conversion Modes
        1. 8.4.3.1 Continuous-Conversion Mode
        2. 8.4.3.2 Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1. 8.5.1.1  Chip Select (CS)
        2. 8.5.1.2  Serial Data Clock (SCLK)
        3. 8.5.1.3  Serial Data Input (DIN)
        4. 8.5.1.4  Serial Data Output (DOUT)
        5. 8.5.1.5  Data Ready (DRDY)
        6. 8.5.1.6  Conversion Synchronization or System Reset (SYNC/RESET)
        7. 8.5.1.7  SPI Communication Frames
        8. 8.5.1.8  SPI Communication Words
        9. 8.5.1.9  ADC Conversion Data
          1. 8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection
        10. 8.5.1.10 Commands
          1. 8.5.1.10.1 NULL (0000 0000 0000 0000)
          2. 8.5.1.10.2 RESET (0000 0000 0001 0001)
          3. 8.5.1.10.3 STANDBY (0000 0000 0010 0010)
          4. 8.5.1.10.4 WAKEUP (0000 0000 0011 0011)
          5. 8.5.1.10.5 LOCK (0000 0101 0101 0101)
          6. 8.5.1.10.6 UNLOCK (0000 0110 0101 0101)
          7. 8.5.1.10.7 RREG (101a aaaa annn nnnn)
            1. 8.5.1.10.7.1 Reading a Single Register
            2. 8.5.1.10.7.2 Reading Multiple Registers
          8. 8.5.1.10.8 WREG (011a aaaa annn nnnn)
        11. 8.5.1.11 Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 ADS131M02-Q1 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Multiple Device Configuration
      5. 9.1.5 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current Shunt Measurement
        2. 9.2.2.2 Battery Pack Voltage Measurement
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 CAP Pin Behavior
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.4 Multiple Device Configuration

Multiple ADS131M02-Q1 devices can be arranged to capture all signals simultaneously. The same clock must be provided to all devices and the SYNC/RESET pins must be strobed simultaneously at least one time to align the sample periods internally between devices. The phase settings of each device can be changed uniquely, but the host must take care to record which channel in the group of devices represents the zero phase.

The devices can also share the SPI bus where only the CS pins for each device are unique. Each device can be addressed sequentially by asserting CS for the device that the host wishes to communicate with. The DOUT pin remains high impedance when the CS pin is high, allowing the DOUT lines to be shared between devices as long as no two devices sharing the bus simultaneously have their CS pins low. Figure 9-3 shows multiple devices configured for simultaneous data acquisition while sharing the SPI bus.

Monitoring the DRDY output of only one of the devices is sufficient because all devices convert simultaneously.

GUID-E9F2E707-A7E4-4737-B9B1-28AC270D6A7D-low.gifFigure 9-3 Multiple Device Configuration