SBAS949A February 2020 – February 2021 ADS131M06
The ADS131M06 receives its clock from the MCU in this design. The ADS131M06 is configured in HR mode and the MCU provides an 8.192-MHz master clock, which is within the allowable clock frequency range for HR mode. The MCU SPI port that is used to communicate with the ADS131M06 is configured to CPOL = 0 and CPHA = 1. The SPI clock frequency is configured to be 8.192 MHz so that all conversion data can be shifted out of the device successfully within the sample period. When powered on, the MCU configures the ADS131M06 registers with the following settings using SPI register writes.
After the ADS131M06 registers are properly initialized, the MCU is configured to generate a GPIO interrupt whenever a falling edge occurs on the DRDY pin, which indicates that the ADS131M06 has new samples available.
The clock fed to the CLKIN pin of the ADS131M06 is internally divided by two to generate the modulator clock. The output data rate of the ADS131M06 is therefore fMOD / OSR = fCLKIN / (2 × OSR) = 8 kSPS.