SBAS949A February 2020 – February 2021 ADS131M06
The master clock can either be sourced externally to the CLKIN pin or generated internally using the onboard oscillator that requires a crystal connected between the XTAL1/CLKIN and XTAL2 pins. For optimal performance, the modulator sampling clock must be synchronous with the serial data clock (SCLK). The modulator sampling clock is derived from the master clock, which means the master clock must be synchronous with SCLK. Therefore, for best performance, supply a master clock to CLKIN and make sure data retrieval is synchronous to the clock signal at CLKIN. When not in use, turn the internal oscillator off to save power.
The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of three power modes: high-resolution (HR) mode, low-power (LP) mode, and very low-power (VLP) mode. Changing the PWR[1:0] bits scales the internal bias currents to achieve the expected power levels. The external clock frequency must follow the guidance provided in the Section 6.3 table corresponding to the intended power mode in order for the device to perform according to the specification.