SBAS603B April 2013 – November 2020 ADS4449
PRODUCTION DATA
At 25°C, AVDD = 1.9 V, AVDD3V = 3.3 V, DRVDD = 1.8 V, rated sampling frequency, 0-dB gain, sine-wave input clock,
1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
Figure 6-34 Spurious-Free Dynamic Range (0-dB Gain)
Figure 6-36 Signal-to-Noise Ratio (0-dB Gain)
Figure 6-35 Spurious-Free Dynamic Range (6-dB Gain)
Figure 6-37 Signal-to-Noise Ratio (6-dB Gain)