1 Features

• Maximum Sample Rate: 100 MSPS
• Programmable Device Resolution
  • Quad-Channel, 16-Bit, High-SNR Mode
  • Quad-Channel, 14-Bit, Low-Power Mode
• 16-Bit High-SNR Mode
  • 1.4 W Total Power at 100 MSPS
    • 355 mW / Channel
  • 4 Vpp Full-scale Input
  • 85-dBFS SNR at f_in = 3 MHz, 100 MSPS
• 14-Bit Low-Power Mode
  • 785 mW Total Power at 100 MSPS
    • 195 mW/Channel
  • 2-Vpp Full-Scale Input
  • 74-dBFS SNR at f_in = 10 MHz
  • Integrated Clamp (for interfacing to CCD sensors)
• Low-Frequency Noise Suppression
• Digital Processing Block
  • Programmable FIR Decimation Filters
  • Programmable Digital Gain: 0 dB to 12 dB
  • 2- or 4-Channel Averaging
• Programmable Mapping Between ADC Input Channels and LVDS Output Pins—Eases Board Design
• Variety of Test Patterns to Verify Data Capture by FPGA/Receiver
• Serialized LVDS Outputs
• Internal and External References
• 3.3-V Analog Supply
• 1.8-V Digital Supply
• Recovers From 6-dB Overload Within 1 Clock Cycle
• Package:
  • 9-mm × 9-mm 64-Pin QFN
  • Non-Magnetic Package Option for MRI Systems
• CMOS Technology

2 Applications

• Medical Imaging – MRI
• Spectroscopy
• CCD Imaging

3 Description

Using CMOS process technology and innovative circuit techniques, the ADS5263 is designed to operate at low power and give very high SNR performance with a 4-Vpp full-scale input. Using a low-noise 16-bit front-end stage followed by a 14-bit ADC, the device gives 85-dBFS SNR up to 10 MHz and better than 80-dBFS SNR up to 30 MHz.

1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Revision History

Changes from C Revision (January 2013) to D Revision

• Added Register 57 in Register Maps Go
• Added Register CB in Register Maps Go
• Added Typical Applications sectionGo
• Added Layout section Go
• Deleted Ordering Information table. See POA at the end of the data sheet. Go

Changes from B Revision (October 2011) to C Revision

• Changed Pin 54 From: REFB To: NCGo
• Changed Pin 55 From: REFC To: NCGo
• Changed the VCM Pin description To: "Internal reference mode: Outputs the common-mode voltage (1.5 V) that can be used externally to bias the analog input External reference mode: Apply voltage input that sets the reference for ADC operation." From: "Outputs the common-mode voltage (1.5 V) that can be used externally to bias the analog input pins."Go
• Added "Idle channel noise" To SNRGo
• Added "Idle channel noise" To LSBGo
• Changed the INL values- 100 MSPS From: TYP = ±2.2 To: ±5, Added MAX = ±12Go
• to Changed the INL values- 80 MSPS From: TYP = ±2.2 To: ±5Go
• Added From: VCM common-mode output voltage To: VCM common-mode output voltage, Internal reference mode Go
• Added From: VCM output current capability To: VCM output current capability, Internal reference modeGo
• Added From: VCM input voltage To: VCM input current, external reference modeGo
• Added VCM input current, external reference mode Typical value - 80 MSPS of 0.5Go
• Changed E_GREF - 100 MSPS MIN value From: ±2.5 To: ±1Go
• Added Temperature Coefficient to E_GREF Go
• Added Temperature Coefficient to E_GCHANGo
• Changed SNR f_in = 5 MHz MIN value From: 68.8 To: to 67.5Go
• Added t_A Aperture delay to the Timing Requirements TableGo
• Changed From: 2 WIRE, 16× SERIALIZATION To: 2 WIRE, 8× SERIALIZATIONGo
• Added 100 MSPS to the SAMPLING FREQUENCY, MSPS column of LVDS Timing at Lower Sampling Frequencies - 2 Wire, 8× SerializationGo
• Changed to 8x from 16xGo
• Changed LVDS Timing for 2 Wire, 7× Serialization title From: LVDS Timing for 2 Wire, 14× Serialization To: LVDS Timing for 2 Wire, 7× SerializationGo
• Changed the Digital Filter SectionGo
• Changed Table 9 Description From: Reference voltage must be forced on REFT and REFB pins To: Apply voltage on VCM pin to set the references for ADC operationGo
• Table 10 Added: <EN_HIGH_ADDRS> as bit D4. Added: Register 0x09 to Serial Register Ma;Go
• Table 10 Added: Register bit EXT_REF_VCM. Added: D12 <18x SERIALIZATION>Go
• Table 10 Added: new register entries from Address 5A to 89. Added: new register F0Go
• Added D4 <EN_HIGH_ADDRS>Go
• Added Added register description table (D10 <EN_CLAMP>) for register 0x09Go
• Added description for register EXT_REF_VCM Go
• Added Description for <EN_REG_42>, <PHASE_DDR> and EXT_REF_VCMGo
• Added Decsription for 18b SERIALIZATIONGo
• Changed D11, D10, and D5 To: SERIALIZATION From: SERIAL'NGo
• Changed the register for A7-A0 IN HEXGo
• Added description for register F0 for A7–A0 IN HEXGo
• Replaced the Clamp Function section with the Clamp Functon for CCD Signals sectionGo
• Deleted Figure - CCD Sensor ConnectionsGo
• Added External Reference ModeGo

Changes from A Revision (August 2011) to B Revision

• Added new Figure below Figure 16Go
• Added new Figure below Figure 22 (now Figure 24)Go
• Added new section below Digital Averaging titled: Performance with Didgital Processing BlocksGo
• Added listitem 6. to the OUTPUT LVDS INTERFACE sectionGo
• Added Added new figure in section Output LVDS Interface (Figure 55)Go
• Added new section after Output LVDS Interface titled: Programmable LCLK Phase, also 2 new figures added.Go
• Added register 42 between register 38 and register 45 Go
• Added new figure 52 in Large and Smll Signal Input Bandwidth sectionGo

Changes from * Revision (May 2011) to A Revision

• Added "Non-Magnetic Package Option for MRI Systems" to FeaturesGo
• Changed Features List Item - From: 1.35 W Total Power at 100 MSPS To: 1.4 W Total Power at 100 MSPSGo
• Changed Features List Item - From: 338 mW / Channel To: 355 mW / ChannelGo
• Changed the CLOCK INPUT values in the ROC tableGo
• Changed the ELECTRICAL CHARACTERISTICS, DYNAMIC PERFORMANCE – 16-BIT ADC tableGo
• Changed the ELECTRICAL CHARACTERISTICS, GENERAL – 16-BIT ADC MODE tableGo
• Added the ELECTRICAL CHARACTERISTICS, DYNAMIC PERFORMANCE – 14-BIT ADC tableGo
• Changed the values in DIGITAL OUTPUTS – LVDS INTERFACEGo
• Added LVDS Timing for 1 Wire 16× Serialization, LVDS Timing for 2 Wire, 7× Serialization, and LVDS Timing for 1 Wire, 14× SerializationGo
• Added Figure 25, Figure 26, and Figure 27Go
• Added section - Large and Small Signal Input BandwidthGo
• Added Section - Board Design ConsiderationsGo
• Added Package Marking ADS5263NM and Ordering Number ADS5263IRGC-NMGo
• Added Section - DEFINITION OF SPECIFICATIONSGo
• Added Section - PackagingGo