8.2.2.1 Clocking Source for ADS5400-SP

The signal to noise ratio of the ADC is limited by three different factors: the quantization noise, the thermal noise, and the total jitter of the sample clock. Quantization noise is driven by the resolution of the ADC, which is 12 bits for the ADS5400. Thermal noise is typically not noticeable in high speed pipelined converters such as the ADS5400-SP, but may be estimated by looking at the signal to noise ratio of the ADC with very low input frequencies and using Equation 4 to solve for thermal noise. (For this estimation, we will take thermal noise to be zero. The lowest frequency for which SNR is specified is 125 MHz. If we had an SNR specification for input frequencies around 5 MHz then that SNR would be a good approximation for SNR due to thermal noise. This would be just an approximation, and the lower the input frequency that has an SNR specification the better this approximation would be.) The thermal noise limits the SNR at low input frequencies while the clock jitter sets the SNR for higher input frequencies. For ADCs with higher resolution and typical SNR of 75 dBFS or so, thermal noise would be more of a factor in overall performance. Quantization noise is also a limiting factor for SNR, as the theoretical maximum achievable SNR as a function of the number of bits of resolution is set by Equation 3.

Equation 3.

where

• N = number of bits resolution.

For a 12-bit ADC, the maximum SNR = 1.76 + (6.02 × 12) = 74 dB. This is the number that we shall enter into Equation 4 for quantization noise as we solve for total SNR for different amounts of clock jitter using Equation 4.

Equation 4.

The SNR limitation due to sample clock jitter can be calculated by Equation 5.

Equation 5.

It is important to note that the clock jitter in Equation 5 is the total amount of clock jitter, whether the jitter source is internal to the ADC itself or external due to the clocking source. The total clock jitter (TJitter) has two components – the internal aperture jitter (125 fs for ADS5400-SP) which is set by the noise of the clock input buffer, and the external clock jitter from the clocking source and all associated buffering of the clock signal. Total clock jitter can be calculated from the aperture jitter and the external clock jitter as in Equation 6.

Equation 6.

External clock jitter can be minimized by using high quality clock sources and jitter cleaners as well as bandpass filters at the clock input while a faster clock slew rate may at times also improve the ADC aperture jitter slightly.

The device has an internal aperture jitter of 125 fs, which is largely fixed. The SNR depending on amount of external jitter for different input frequencies is shown in Figure 40. Often the design requirements will list a target SNR for a system, and Equation 4 through Equation 6 are then used to calculate the external clock jitter needed from the clocking solution to meet the system objectives.

Figure 40 shows that with an external clock jitter of 200 fs rms, the expected SNR of the device would be greater than 58 dBFS at an input tone of 400 MHz, which is the assumed bandwidth for this design example. Having less external clock jitter such as 150 fs rms or even 100 fs rms would result in an SNR that would exceed our design target, but at possibly the expense of a more costly clocking solution. Having external clock jitter of much greater than 200 fs rms or more would fail to meet our design target.