ADS54J66 datasheet

SBAS745A November 2015 – December 2015 ADS54J66

PRODUCTION DATA.

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Mechanical Data (Package|Pins)

RMP|72
- MPQF396A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sbas745a_oa

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Start-Up Sequence

The following steps are recommended as the power-up sequence with the ADS54J66 in DDC mode 8 (no decimation) with LMFS = 4421 (shown in Table 72).

Table 72. Recommended Power-Up Sequence

STEP	DESCRIPTION	REGISTER ADDRESS	REGISTER DATA	COMMENT
1	Supply all supply voltages. There is no required power supply sequence for the 1.15-V supply, 1.9-V supply, and 3-V supply, and they can be supplied in any order.	—	—	—
2	Pulse a hardware reset (low to high to low) on pin 48.	—	—	—
2	Alternatively, the device can be reset with an analog reset and a digital reset.	0000h 4004h 4003h 4002h 4001h 60F7h 60F7h 70F7h 70F7h	81h 68h 00h 00h 00h 01h 00h 01h 00h	—
3	Set the input clock divider.	0011h 0053h 0039h 0059h	80h 80h C0h 20h	Select the master page in the analog bank. Set the clock divider to divide-by-2. Set the ALWAYS WRITE 1 bit for all channels. Set the ALWAYS WRITE 1 bit for all channels.
4	Reset the interleaving correction engine in register 6800h of the main digital page of the JESD bank. (Register access is already set to page 6800h in step 2.)	6000h 6000h 7000h 7000h	01h 00h 01h 00h	Resets the interleaving engine for channel A, B (because the device is in broadcast mode). Resets the interleaving engine for channel C, D (because the device is in broadcast mode).
5	Set DDC mode 8 for all channels (no decimation, 14-bit, 500-MSPS data output).	4004h 4003h	61h 41h	Select the decimation filter page of the JESD bank.
		6000h 7000h	08h 08h	Select DDC mode 8 for channel A, B. Select DDC mode 8 for channel C, D.
		6001h 7001h	04h 04h	Set the ALWAYS WRITE 1 bit for channel A, B. Set the ALWAYS WRITE 1 bit for channel C, D.
6	Default registers for the analog page of the JESD bank.	4003h 4004h	00h 6Ah	Select the analog page in the JESD bank.
6	Default registers for the analog page of the JESD bank.	6016h 7016h	02h 02h	PLL mode 40x for channel A, B. PLL mode 40x for channel C, D.
7	Default registers for the digital page of the JESD bank.	4003h 4004h	00h 69h	Select the digital page in the JESD bank.
		6000h 6001h 7000h 7001h	20h 01h 20h 01h	Enable JESD MODE control for channel A, B. Set JESD MODE to 20x mode for LMFS = 4421. Enable JESD MODE control for channel C, D. Set JESD MODE to 20x mode for LMFS = 4421.
		6000h 6006h 7000h 7006h	80h 0Fh 80h 0Fh	Set CTRL K for channel A, B. Set K to 16. Set CTRL K for channel C, D. Set K to 16.
8	Enable a single SYNCb input (on the SYNCbAB pin).	4005h 7001h	01h 20h	Disable broadcast mode. Use SYNCbABP, SYNCbABM to issue a SYNC request for all four channels.
9	Pulse SYNCbAB (pins 55 and 56) from high to low.	—	—	K28.5 characters are transmitted by all four channels (CGS phase).
10	Pulse SYNCbAB (pins 55 and 56) from low to high.	—	—	The ILA sequence begins and lasts for four multiframes. The device transmits ADC data after the ILA sequence ends.

8.1.2 Hardware Reset

8.1.2.1 Register Initialization

After power-up, the internal registers can be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 142. Alternatively, the serial interface registers can be cleared a set of register writes as described in the Start-Up Sequence section. Table 73 lists the timing requirements for the pulse signal on the RESET pin.

ADS54J66 hardware_reset_tmng_dgm_sbas706.gif

Figure 142. Hardware Reset Timing Diagram

Table 73. Timing Requirements for Hardware Reset

		MIN	UNIT
t₁	Power-on delay from power-up to active high RESET pulse	1	ms
t₂	Reset pulse duration : active high RESET pulse duration	10	ns
t₃	Register write delay from RESET disable to SEN active	100	ns

8.1.3 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors (as shown in Equation 2): the quantization noise is typically not noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input frequencies and the clock jitter sets the SNR for higher input frequencies.

Equation 2. ADS54J66 sgnl_to_noise_ratio_eq_sbas706.png

The SNR limitation resulting from sample clock jitter can be calculated by Equation 3:

Equation 3. ADS54J66 snr_limitation_eq_sbas706.png

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (120 fs for the ADS54J66) that is set by the noise of the clock input buffer and the external clock jitter. T_Jitter can be calculated by Equation 4:

Equation 4. ADS54J66 total_jitter_eq_sbas706.png

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input; a faster clock slew rate also improves the ADC aperture jitter.

The ADS54J66 has a thermal noise of approximately 72 dBFS and an internal aperture jitter of 120 fs.

8.1.4 ADC Test Pattern

The ADS54J66 provides several different options to output test patterns instead of the actual output data of the ADC in order to simplify bring up of the JESD204B digital interface link. The output data path is shown in Figure 143.

Figure 143. ADC Test Pattern

8.1.4.1 ADC Section

The ADC test pattern replaces the actual output data of the ADC. The following test patterns are available in register 74h. In order to properly obtain the test pattern output, the interleaving correction must be disabled (6100h, address 18h) and DDC mode-8 must be selected (un-decimated output).

In un-decimated output (DDC mode-8), the device supports LMFS = 4421 only. Available ADC test patterns are summarized in Table 74.

Table 74. ADC Test Pattern Settings

BIT	NAME	DEFAULT	DESCRIPTION
7-4	TEST PATTERN	0000	These bits provide the test pattern output on channels A and B. 0000 = Normal operation using ADC output data 0001 = Outputs all 0s 0010 = Outputs all 1s 0011 = Outputs toggle pattern: output data are an alternating sequence of 101010101010 and 010101010101 0100 = Output digital ramp: output data increment by one LSB every clock cycle from code 0 to 16384 0110 = Single pattern: output data are custom pattern 1 (75h and 76h) 0111 = Double pattern: output data alternate between custom pattern 1 and custom pattern 2 1000 = Deskew pattern: output data are 2AAAh 1001 = SYNC pattern: output data are 3FFFh

8.1.4.2 Transport Layer Pattern

The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the LMFS parameters. Tail bits or 0s are added when needed. Alternatively, the JESD204B long transport layer test pattern can be substituted as shown in Table 75.

Table 75. Transport Layer Test Mode

BIT	NAME	DEFAULT	DESCRIPTION
4	TESTMODE EN	0	This bit generates the long transport layer test pattern mode according to clause 5.1.6.3 of the JESD204B specification. 0 = Test mode disabled 1 = Test mode enabled

8.1.4.3 Link Layer Pattern

The link layer contains the scrambler and the 8b/10b encoding of any data passed on from the transport layer. Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted. The link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test patterns do not pass through the 8b/10b encoder and contain the options shown in Table 76.

Table 76. Link Layer Test Mode

BIT	NAME	DEFAULT	DESCRIPTION
7-5	LINK LAYER TESTMODE	000	These bits generate the pattern according to clause 5.3.3.8.2 of the JESD204B document. 000 = Normal ADC data 001 = D21.5 (high-frequency jitter pattern) 010 = K28.5 (mixed-frequency jitter pattern) 011 = Repeat initial lane alignment (generates a K28.5 character and repeats lane alignment sequences continuously) 100 = 12-octet RPAT jitter pattern

Furthermore, a 2¹⁵ PRBS can be enabled by setting up a custom test pattern (AAAA) in the ADC section and running that through the 8b/10b encoder with scrambling enabled.

8.2 Typical Application

The ADS54J66 is designed for wideband receiver applications demanding excellent dynamic range over a large input frequency range. A typical schematic for an ac-coupled dual receiver (dual FPGA with dual SYNC) is shown in Figure 144.

NOTE:

GND = AGND and DGND are connected in the PCB layout.

Figure 144. Application Diagram for the ADS54J66

8.2.1 Design Requirements

By using the simple drive circuit of Figure 144 (when the amplifier drives the ADC) or Figure 51 (when transformers drive the ADC), uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

8.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves the common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 144.

8.2.3 Application Curves

Figure 145 and Figure 146 show the typical performance at 190 MHz and 230 MHz, respectively.

f_IN = 190 MHz, A_IN = –1 dBFS,
SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (non 23)

Figure 145. FFT for 190-MHz Input Signal

f_IN = 230 MHz, A_IN = –1 dBFS,
SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (non 23)

Figure 146. FFT for 230-MHz Input Signal