SBAS745A November   2015  – December 2015 ADS54J66

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  AC Performance
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Typical Characteristics: General (DDC Mode-8)
    10. 6.10 Typical Characteristics: Mode 2
    11. 6.11 Typical Characteristics: Mode 0
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Recommended Input Circuitry
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Features
      2. 7.4.2 Mode 0, Decimation-by-2 with IQ Outputs for up to 220 MHz of IQ Bandwidth
      3. 7.4.3 Mode 2, Decimation-by-2 for up to 110 MHz of Real Bandwidth
      4. 7.4.4 Modes 4 and 7, Decimation-by-2 with Real Outputs for up to 110 MHz of Bandwidth
      5. 7.4.5 Mode 5, Decimation-by-2 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      6. 7.4.6 Mode 6, Decimation-by-4 with IQ Outputs for up to 110 MHz of IQ Bandwidth
      7. 7.4.7 Overrange Indication
      8. 7.4.8 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 Device Configuration
        1. 7.5.1.1 Details of the Serial Interface
        2. 7.5.1.2 Serial Register Write: Analog Bank
        3. 7.5.1.3 Serial Register Readout: Analog Bank
        4. 7.5.1.4 JESD Bank SPI Page Selection
        5. 7.5.1.5 Serial Register Write: Digital Bank
        6. 7.5.1.6 Individual Channel Programming
        7. 7.5.1.7 Serial Register Readout: JESD Bank
      2. 7.5.2 JESD204B Interface
        1. 7.5.2.1 JESD204B Initial Lane Alignment (ILA)
        2. 7.5.2.2 JESD204B Frame Assembly
        3. 7.5.2.3 JESD Output Switch
          1. 7.5.2.3.1 SERDES Transmitter Interface
          2. 7.5.2.3.2 SYNCb Interface
          3. 7.5.2.3.3 Eye Diagram
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Information
      2. 7.6.2 Example Register Writes
      3. 7.6.3 Register Descriptions
        1. 7.6.3.1 General Registers
          1. 7.6.3.1.1 Register 0h (offset = 0h) [reset = 0h]
          2. 7.6.3.1.2 Register 3h, 4h (offset = 3h, 4h) [reset = 0h]
          3. 7.6.3.1.3 Register 5h (offset = 5h) [reset = 0h]
          4. 7.6.3.1.4 Register 11h (offset = 11h) [reset = 0h]
        2. 7.6.3.2 Master Page (80h)
          1. 7.6.3.2.1  Register 20h (address = 20h) [reset = 0h], Master Page (080h)
          2. 7.6.3.2.2  Register 21h (address = 21h) [reset = 0h], Master Page (080h)
          3. 7.6.3.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 7.6.3.2.4  Register 24h (address = 24h) [reset = 0h], Master Page (080h)
          5. 7.6.3.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 7.6.3.2.6  Register 3Ah (address = 3Ah) [reset = 0h], Master Page (80h)
          7. 7.6.3.2.7  Register 39h (address = 39h) [reset = 0h], Master Page (80h)
          8. 7.6.3.2.8  Register 53h (address = 53h) [reset = 0h], Master Page (80h)
          9. 7.6.3.2.9  Register 55h (address = 55h) [reset = 0h], Master Page (80h)
          10. 7.6.3.2.10 Register 56h (address = 56h) [reset = 0h], Master Page (80h)
          11. 7.6.3.2.11 Register 59h (address = 59h) [reset = 0h], Master Page (80h)
        3. 7.6.3.3 ADC Page (0Fh)
          1. 7.6.3.3.1  Register 5Fh (address = 5Fh) [reset = 0h], ADC Page (0Fh)
          2. 7.6.3.3.2  Register 60h (address = 60h) [reset = 0h], ADC Page (0Fh)
          3. 7.6.3.3.3  Register 61h (address = 61h) [reset = 0h], ADC Page (0Fh)
          4. 7.6.3.3.4  Register 6Ch (address = 6Ch) [reset = 0h], ADC Page (0Fh)
          5. 7.6.3.3.5  Register 6Dh (address = 6Dh) [reset = 0h], ADC Page (0Fh)
          6. 7.6.3.3.6  Register 74h (address = 74h) [reset = 0h], ADC Page (0Fh)
          7. 7.6.3.3.7  Register 75h (address = 75h) [reset = 0h], ADC Page (0Fh)
          8. 7.6.3.3.8  Register 76h (address = 76h) [reset = 0h], ADC Page (0Fh)
          9. 7.6.3.3.9  Register 77h (address = 77h) [reset = 0h], ADC Page (0Fh)
          10. 7.6.3.3.10 Register 78h (address = 78h) [reset = 0h], ADC Page (0Fh)
        4. 7.6.3.4 Interleaving Engine Page (6100h)
          1. 7.6.3.4.1 Register 18h (address = 18h) [reset = 0h], Interleaving Engine Page (6100h)
          2. 7.6.3.4.2 Register 68h (address = 68h) [reset = 0h], Interleaving Engine Page (6100h)
        5. 7.6.3.5 Decimation Filter Page (6141h) Registers
          1. 7.6.3.5.1 Register 0h (address = 0h) [reset = 0h], Decimation Filter Page (6141h)
          2. 7.6.3.5.2 Register 1h (address = 1h) [reset = 0h], Decimation Filter Page (6141h)
          3. 7.6.3.5.3 Register 2h (address = 2h) [reset = 0h], Decimation Filter Page (6141h)
        6. 7.6.3.6 Main Digital Page (6800h) Registers
          1. 7.6.3.6.1 Register 0h (address = 0h) [reset = 0h], Main Digital Page (6800h)
          2. 7.6.3.6.2 Register 42h (address = 42h) [reset = 0h], Main Digital Page (6800h)
          3. 7.6.3.6.3 Register 4Eh (address = 4Eh) [reset = 0h], Main Digital Page (6800h)
          4. 7.6.3.6.4 Register ABh (address = ABh) [reset = 0h], Main Digital Page (6800h)
          5. 7.6.3.6.5 Register ADh (address = ADh) [reset = 0h], Main Digital Page (6800h)
          6. 7.6.3.6.6 Register F7h (address = F7h) [reset = 0h], Main Digital Page (68h)
        7. 7.6.3.7 JESD Digital Page (6900h) Registers
          1. 7.6.3.7.1  Register 0h (address = 0h) [reset = 0h], JESD Digital Page (6900h)
          2. 7.6.3.7.2  Register 1h (address = 1h) [reset = 0h], JESD Digital Page (6900h)
          3. 7.6.3.7.3  Register 2h (address = 2h) [reset = 0h], JESD Digital Page (6900h)
          4. 7.6.3.7.4  Register 3h (address = 3h) [reset = 0h], JESD Digital Page (6900h)
          5. 7.6.3.7.5  Register 5h (address = 5h) [reset = 0h], JESD Digital Page (6900h)
          6. 7.6.3.7.6  Register 6h (address = 6h) [reset = 0h], JESD Digital Page (6900h)
          7. 7.6.3.7.7  Register 19h (address = 19h) [reset = 0h], JESD Digital Page (6900h)
          8. 7.6.3.7.8  Register 1Ah (address = 1Ah) [reset = 0h], JESD Digital Page (6900h)
          9. 7.6.3.7.9  Register 1Bh (address = 1Bh) [reset = 0h], JESD Digital Page (6900h)
          10. 7.6.3.7.10 Register 1Ch (address = 1Ch) [reset = 0h], JESD Digital Page (6900h)
          11. 7.6.3.7.11 Register 1Dh (address = 1Dh) [reset = 0h], JESD Digital Page (6900h)
          12. 7.6.3.7.12 Register 1Eh (address = 1Eh) [reset = 0h], JESD Digital Page (6900h)
          13. 7.6.3.7.13 Register 1Fh (address = 1Fh) [reset = 0h], JESD Digital Page (6900h)
          14. 7.6.3.7.14 Register 20h (address = 20h) [reset = 0h], JESD Digital Page (6900h)
          15. 7.6.3.7.15 Register 21h (address = 21h) [reset = 0h], JESD Digital Page (6900h)
          16. 7.6.3.7.16 Register 22h (address = 22h) [reset = 0h], JESD Digital Page (6900h)
        8. 7.6.3.8 JESD Analog Page (6A00h) Register
          1. 7.6.3.8.1 Register 12h, 13h (address 12h, 13h) [reset = 0h], JESD Analog Page (6Ah)
          2. 7.6.3.8.2 16h (address = 16h) [reset = 0h], JESD Analog Page (6A00h)
          3. 7.6.3.8.3 Register 1Bh (address = 1Bh) [reset = 0h], JESD Analog Page (6Ah)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Start-Up Sequence
      2. 8.1.2 Hardware Reset
        1. 8.1.2.1 Register Initialization
      3. 8.1.3 SNR and Clock Jitter
      4. 8.1.4 ADC Test Pattern
        1. 8.1.4.1 ADC Section
        2. 8.1.4.2 Transport Layer Pattern
        3. 8.1.4.3 Link Layer Pattern
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Start-Up Sequence

The following steps are recommended as the power-up sequence with the ADS54J66 in DDC mode 8 (no decimation) with LMFS = 4421 (shown in Table 72).

Table 72. Recommended Power-Up Sequence

STEP DESCRIPTION REGISTER ADDRESS REGISTER DATA COMMENT
1 Supply all supply voltages. There is no required power supply sequence for the 1.15-V supply, 1.9-V supply, and 3-V supply, and they can be supplied in any order.
2 Pulse a hardware reset (low to high to low) on pin 48.
Alternatively, the device can be reset with an analog reset and a digital reset. 0000h
4004h
4003h
4002h
4001h
60F7h
60F7h
70F7h
70F7h
81h
68h
00h
00h
00h
01h
00h
01h
00h
3 Set the input clock divider. 0011h
0053h
0039h
0059h
80h
80h
C0h
20h
Select the master page in the analog bank.
Set the clock divider to divide-by-2.
Set the ALWAYS WRITE 1 bit for all channels.
Set the ALWAYS WRITE 1 bit for all channels.
4 Reset the interleaving correction engine in register 6800h of the main digital page of the JESD bank. (Register access is already set to page 6800h in step 2.) 6000h
6000h
7000h
7000h
01h
00h
01h
00h
Resets the interleaving engine for channel A, B (because the device is in broadcast mode).
Resets the interleaving engine for channel C, D (because the device is in broadcast mode).
5 Set DDC mode 8 for all channels (no decimation, 14-bit, 500-MSPS data output). 4004h
4003h
61h
41h
Select the decimation filter page of the JESD bank.
6000h
7000h
08h
08h
Select DDC mode 8 for channel A, B.
Select DDC mode 8 for channel C, D.
6001h
7001h
04h
04h
Set the ALWAYS WRITE 1 bit for channel A, B.
Set the ALWAYS WRITE 1 bit for channel C, D.
6 Default registers for the analog page of the JESD bank. 4003h
4004h
00h
6Ah
Select the analog page in the JESD bank.
6016h
7016h
02h
02h
PLL mode 40x for channel A, B.
PLL mode 40x for channel C, D.
7 Default registers for the digital page of the JESD bank. 4003h
4004h
00h
69h
Select the digital page in the JESD bank.
6000h
6001h
7000h
7001h
20h
01h
20h
01h
Enable JESD MODE control for channel A, B.
Set JESD MODE to 20x mode for LMFS = 4421.
Enable JESD MODE control for channel C, D.
Set JESD MODE to 20x mode for LMFS = 4421.
6000h
6006h
7000h
7006h
80h
0Fh
80h
0Fh
Set CTRL K for channel A, B.
Set K to 16.
Set CTRL K for channel C, D.
Set K to 16.
8 Enable a single SYNCb input (on the SYNCbAB pin). 4005h
7001h
01h
20h
Disable broadcast mode.
Use SYNCbABP, SYNCbABM to issue a SYNC request for all four channels.
9 Pulse SYNCbAB (pins 55 and 56) from high to low. K28.5 characters are transmitted by all four channels (CGS phase).
10 Pulse SYNCbAB (pins 55 and 56) from low to high. The ILA sequence begins and lasts for four multiframes. The device transmits ADC data after the ILA sequence ends.

8.1.2 Hardware Reset

8.1.2.1 Register Initialization

After power-up, the internal registers can be initialized to their default values through a hardware reset by applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 142. Alternatively, the serial interface registers can be cleared a set of register writes as described in the Start-Up Sequence section. Table 73 lists the timing requirements for the pulse signal on the RESET pin.

ADS54J66 hardware_reset_tmng_dgm_sbas706.gif Figure 142. Hardware Reset Timing Diagram

Table 73. Timing Requirements for Hardware Reset

MIN TYP MAX UNIT
t1 Power-on delay from power-up to active high RESET pulse 1 ms
t2 Reset pulse duration : active high RESET pulse duration 10 ns
t3 Register write delay from RESET disable to SEN active 100 ns

8.1.3 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors (as shown in Equation 2): the quantization noise is typically not noticeable in pipeline converters and is 84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input frequencies and the clock jitter sets the SNR for higher input frequencies.

Equation 2. ADS54J66 sgnl_to_noise_ratio_eq_sbas706.png

The SNR limitation resulting from sample clock jitter can be calculated by Equation 3:

Equation 3. ADS54J66 snr_limitation_eq_sbas706.png

The total clock jitter (TJitter) has two components: the internal aperture jitter (120 fs for the ADS54J66) that is set by the noise of the clock input buffer and the external clock jitter. TJitter can be calculated by Equation 4:

Equation 4. ADS54J66 total_jitter_eq_sbas706.png

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass filters at the clock input; a faster clock slew rate also improves the ADC aperture jitter.

The ADS54J66 has a thermal noise of approximately 72 dBFS and an internal aperture jitter of 120 fs.

8.1.4 ADC Test Pattern

The ADS54J66 provides several different options to output test patterns instead of the actual output data of the ADC in order to simplify bring up of the JESD204B digital interface link. The output data path is shown in Figure 143.

ADS54J66 ADC_tst_Pttrn_sbas745.gif Figure 143. ADC Test Pattern

8.1.4.1 ADC Section

The ADC test pattern replaces the actual output data of the ADC. The following test patterns are available in register 74h. In order to properly obtain the test pattern output, the interleaving correction must be disabled (6100h, address 18h) and DDC mode-8 must be selected (un-decimated output).

In un-decimated output (DDC mode-8), the device supports LMFS = 4421 only. Available ADC test patterns are summarized in Table 74.

Table 74. ADC Test Pattern Settings

BIT NAME DEFAULT DESCRIPTION
7-4 TEST PATTERN 0000 These bits provide the test pattern output on channels A and B.
0000 = Normal operation using ADC output data
0001 = Outputs all 0s
0010 = Outputs all 1s
0011 = Outputs toggle pattern: output data are an alternating sequence of 101010101010 and 010101010101
0100 = Output digital ramp: output data increment by one LSB every clock cycle from code 0 to 16384
0110 = Single pattern: output data are custom pattern 1 (75h and 76h)
0111 = Double pattern: output data alternate between custom pattern 1 and custom pattern 2
1000 = Deskew pattern: output data are 2AAAh
1001 = SYNC pattern: output data are 3FFFh

8.1.4.2 Transport Layer Pattern

The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the LMFS parameters. Tail bits or 0s are added when needed. Alternatively, the JESD204B long transport layer test pattern can be substituted as shown in Table 75.

Table 75. Transport Layer Test Mode

BIT NAME DEFAULT DESCRIPTION
4 TESTMODE EN 0 This bit generates the long transport layer test pattern mode according to clause 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled

8.1.4.3 Link Layer Pattern

The link layer contains the scrambler and the 8b/10b encoding of any data passed on from the transport layer. Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted. The link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test patterns do not pass through the 8b/10b encoder and contain the options shown in Table 76.

Table 76. Link Layer Test Mode

BIT NAME DEFAULT DESCRIPTION
7-5 LINK LAYER TESTMODE 000 These bits generate the pattern according to clause 5.3.3.8.2 of the JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character and repeats lane alignment sequences continuously)
100 = 12-octet RPAT jitter pattern

Furthermore, a 215 PRBS can be enabled by setting up a custom test pattern (AAAA) in the ADC section and running that through the 8b/10b encoder with scrambling enabled.

8.2 Typical Application

The ADS54J66 is designed for wideband receiver applications demanding excellent dynamic range over a large input frequency range. A typical schematic for an ac-coupled dual receiver (dual FPGA with dual SYNC) is shown in Figure 144.

ADS54J66 typ_app_sbas745.gif

NOTE:

GND = AGND and DGND are connected in the PCB layout.
Figure 144. Application Diagram for the ADS54J66

8.2.1 Design Requirements

By using the simple drive circuit of Figure 144 (when the amplifier drives the ADC) or Figure 51 (when transformers drive the ADC), uniform performance can be obtained over a wide frequency range. The buffers present at the analog inputs of the device help isolate the external drive source from the switching currents of the sampling circuit.

8.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves the common-mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 144.

8.2.3 Application Curves

Figure 145 and Figure 146 show the typical performance at 190 MHz and 230 MHz, respectively.

ADS54J66 D003_SBAS717.gif
fIN = 190 MHz, AIN = –1 dBFS,
SNR = 69.4 dBFS, SFDR = 88 dBc, SFDR = 96 dBc (non 23)
Figure 145. FFT for 190-MHz Input Signal
ADS54J66 D004_SBAS717.gif
fIN = 230 MHz, AIN = –1 dBFS,
SNR = 69.4 dBFS, SFDR = 85 dBc, SFDR = 96 dBc (non 23)
Figure 146. FFT for 230-MHz Input Signal